On 06/10/2017 19:25, Radim Krčmář wrote: > Various bugs that incorrectly injected a timer interrupt. > > Going to work on kvm-unit-tests for this too. > > > Radim Krčmář (3): > KVM: x86: handle 0 write to TSC_DEADLINE MSR > KVM: x86: really disarm lapic timer when clearing TMICT > KVM: x86: thoroughly disarm LAPIC timer around TSC deadline switch > > arch/x86/kvm/lapic.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > Queued, thanks. Paolo
