2017-10-05 18:54-0700, Wanpeng Li:
> From: Wanpeng Li <wanpeng.li@xxxxxxxxxxx>
>
> If we take TSC-deadline mode timer out of the picture, the Intel SDM
> does not say that the timer is disable when the timer mode is change,
> either from one-shot to periodic or vice versa.
>
> After this patch, the timer is no longer disarmed on change of mode, so
> the counter (TMCCT) keeps counting down.
>
> So what does a write to LVTT changes ? On baremetal, the change of mode
> is probably taken into account only when the counter reach 0. When this
> happen, LVTT is use to figure out if the counter should restard counting
> down from TMICT (so periodic mode) or stop counting (if one-shot mode).
>
> This patch is based on observation of the behavior of the APIC timer on
> baremetal as well as check that they does not go against the description
> written in the Intel SDM.
>
> Cc: Paolo Bonzini <pbonzini@xxxxxxxxxx>
> Cc: Radim Krčmář <rkrcmar@xxxxxxxxxx>
> Signed-off-by: Wanpeng Li <wanpeng.li@xxxxxxxxxxx>
> ---
> arch/x86/kvm/lapic.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
Queued the first two patches, thanks.
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 8841bb5..14f63b3 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -1329,10 +1329,14 @@ static void apic_update_lvtt(struct kvm_lapic *apic)
>
> if (apic->lapic_timer.timer_mode != timer_mode) {
> if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
> - APIC_LVT_TIMER_TSCDEADLINE))
> + APIC_LVT_TIMER_TSCDEADLINE)) {
> kvm_lapic_set_reg(apic, APIC_TMICT, 0);
> + hrtimer_cancel(&apic->lapic_timer.timer);
> + }
> + if (apic_lvtt_oneshot(apic) && (timer_mode ==
> + APIC_LVT_TIMER_PERIODIC))
> + limit_periodic_timer_frequency(apic);
> apic->lapic_timer.timer_mode = timer_mode;
> - hrtimer_cancel(&apic->lapic_timer.timer);
> }
> }
>
> --
> 2.7.4
>
