On Tue, May 19, 2009 at 05:18:07PM +0200, Alexander Graf wrote: > > On 19.05.2009, at 15:58, Marcelo Tosatti wrote: > >> On Tue, May 19, 2009 at 04:56:48PM +0300, Avi Kivity wrote: >>> Marcelo Tosatti wrote: >>>>> I think that for ASID!=0 you can actually do nothing. The guest >>>>> entry is a cr3 switch, so we'll both get a tlb flush and a >>>>> resync on >>>>> any modified ptes. >>>>> >>>>> For ASID==0 you can do the invlpg thing. >>>>> >>>>> Marcelo? >>>>> >>>> >>>> kvm_mmu_invlpg is cheap, better just invalidate the entry. If >>>> hyper-v >>>> uses invlpga to invalidate TLB entries which it has updated pte's in >>>> memory for, and you skip the invalidation now and somehow later >>>> use an >>>> unsync spte, you're toast. >>>> >>> >>> But won't the guest entry cause a resync? >> >> If its a cr3/cr4 exit, yes. > > Well it has to be. Either we're switching from one NPT to the other > (todo) or do a normal cr3+cr4 switch. > > So I guess we can optimize here. Is it worth it? IMHO better leave it the way it is, perhaps add a comment that the optimization is possible, and do it later if worthwhile. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
