From: Alex Williamson > Sent: 16 August 2017 17:56 ... > Firmware pissing match... Processors running with 8k or less page size > fall within the recommendations of the PCI spec for register alignment > of MMIO regions of the device and this whole problem becomes less of an > issue. Actually if qemu is causing the MSI-X table accesses to fault, why doesn't it just lie to the guest about the physical address of the MSI-X table? Then mmio access to anything in the same physical page will just work. It has already been pointed out that you can't actually police the interrupts that are raised without host hardware support. Actually, putting other vectors in the MSI-X table is boring, most drivers will ignore unexpected interrupts. Much more interesting are physical memory addresses and accessible IO addresses. Of course, a lot of boards have PCI master capability and can probably be persuaded to do writes to specific location anyway. David
