On 12/08/2017 15:35, Yu Zhang wrote: > Intel's existing processors limit the maximum linear address width to > 48 bits, and the maximum physical address width to 46 bits. And the > upcoming processors will extend maximum linear address width to 57 bits > and maximum physical address width can go upto 52 bits in practical. > > With linear address width greater than 48, a new paging mode in IA-32e > is introduced - 5 level paging(also known as LA57). And to support VMs > with this feature, KVM MMU code need to be extended. > > And to achieve this, this patchset: > 1> leverages 2 qemu parameters: +la57 and phys-bits to expose wider linear > address width and physical address width to the VM; > 2> extends shadow logic to construct 5 level shadow page for VMs running > in LA57 mode; > 3> extends ept logic to construct 5 level ept table for VMs whose maximum > physical width exceeds 48 bits. Thanks, this looks good. I only had a few suggestions in my reply to patch 3. Paolo
