> > A] Problems to solve: > > ------------------ > > > > 1] We are considering two approaches for 'fake DAX flushing interface'. > > > > 1.1] fake dax with NVDIMM flush hints & KVM async page fault > > > > - Existing interface. > > > > - The approach to use flush hint address is already nacked upstream. > > > > - Flush hint not queued interface for flushing. Applications might > > avoid to use it. > > This doesn't contradicts the last point about async operation and vcpu > control. KVM async page faults turn the Address Flush Hints write into > an async operation so the guest can get other work done while waiting > for completion. > > > > > - Flush hint address traps from guest to host and do an entire fsync > > on backing file which itself is costly. > > > > - Can be used to flush specific pages on host backing disk. We can > > send data(pages information) equal to cache-line size(limitation) > > and tell host to sync corresponding pages instead of entire disk > > sync. > > Are you sure? Your previous point says only the entire device can be > synced. The NVDIMM Adress Flush Hints interface does not involve > address range information. Just syncing entire block device should be simple but costly. Using flush hint address to write data which contains list/info of dirty pages to flush requires more thought. This calls mmio write callback at Qemu side. As per Intel (ACPI spec 6.1, Table 5-135) there is limit to max length of data guest can write and is equal to cache line size. > > > > > - This will be an asynchronous operation and vCPU control is returned > > quickly. > > > > > > 1.2] Using additional para virt device in addition to pmem device(fake dax > > with device flush) > > Perhaps this can be exposed via ACPI as part of the NVDIMM standards > instead of a separate KVM-only paravirt device. Same reason as above. If we decide on sending list of dirty pages there is limit to send max size of data to host using flush hint address. >
