> @@ -8358,7 +8349,7 @@ static int vmx_handle_exit(struct kvm_vcpu *vcpu) > * mode as if vcpus is in root mode, the PML buffer must has been > * flushed already. > */ > - if (enable_pml) > + if (enable_pml && !is_guest_mode(vcpu)) > vmx_flush_pml_buffer(vcpu); > > /* If guest state is invalid, start emulating */ I don't understand this. You need to flush the PML buffer if L2 is running with EPT A/D bits enabled, don't you? Apart from this it seems sane, I only have to look at patch 3 more carefully. Thanks, Paolo
