On Thu, May 11, 2017 at 10:30 AM, Paolo Bonzini <pbonzini@xxxxxxxxxx> wrote:
>
>
> ----- Original Message -----
>> From: "Peter Feiner" <pfeiner@xxxxxxxxxx>
>> To: "Paolo Bonzini" <pbonzini@xxxxxxxxxx>
>> Cc: kvm@xxxxxxxxxxxxxxx, "David Matlack" <dmatlack@xxxxxxxxxx>
>> Sent: Thursday, May 11, 2017 5:58:49 PM
>> Subject: Re: [PATCH kvm-unit-tests 2/2] vmx: fix expected results of new EPT tests
>>
>> On Thu, May 11, 2017 at 4:23 AM, Paolo Bonzini <pbonzini@xxxxxxxxxx> wrote:
>> > Remove RD/EX exchange hack which we can fix in KVM; mark page table
>> > accesses as read/write when EPT A/D is enabled, and expect them to
>> > be handled as read/write even with disabled EPT A/D bits (even though
>> > the exit qualification says otherwise).
>>
>> I assume this is a stopgap change. I mean, you're asserting for the
>> wrong behavior just so the tests pass. Correct?
>
> No, I've tried the tests on upstream Linux with eptad=0 (so that EPT A/D
> is not used by KVM on the host) and they also hang with an infinite stream
> of EPT violations.
I think the failures are caused by this code in handle_ept_violation,
which clears the ACC_WRITE bit of the exit qualification before
handling the fault, when EPT A/D is disabled:
if (is_guest_mode(vcpu)
&& !(exit_qualification & EPT_VIOLATION_GVA_TRANSLATED)) {
/*
* Fix up exit_qualification according to whether guest
* page table accesses are reads or writes.
*/
u64 eptp = nested_ept_get_cr3(vcpu);
if (!(eptp & VMX_EPT_AD_ENABLE_BIT))
exit_qualification &= ~EPT_VIOLATION_ACC_WRITE;
}
Per 28.2.3.2 EPT Violations: "Writes by the logical processor to guest
paging structures to update accessed and dirty flags are considered to
be data writes." In other words, it's valid for
EPT_VIOLATION_GVA_TRANSLATED and EPT_VIOLATION_ACC_WRITE to both be
set in the exit qual when EPT A/D is disabled.
> See the KVM patch I sent which also explains the hang
> in the comments ("[PATCH 2/2] KVM: nVMX: fix nEPT handling of guest page
> table accesses").
>
> So it seems to me that this is the expected behavior of the processor
> even when A/D bits are disabled. I haven't tested on a processor with
> EPT but without A/D bits though.
>
> Paolo
