Hi Michael, On 02/05/2017 19:36, Michael S. Tsirkin wrote: > On Tue, May 02, 2017 at 09:30:39AM +0200, Auger Eric wrote: >> Hi Will, Robin, Jean-Philippe, >> >> I have been working on the integration between user-space emulated >> SMMU-v3 and VFIO in QEMU. At the moment I fail identifying a proper easy >> way to trap page table updates. This is requested to keep the host >> translation structures consistent to guest translation structures. >> >> On Intel VTD there is a so-called "caching mode" (CM, see VTD spec >> paragraph 6.1) that forces the OS to explicitly invalidate caches >> whenever it updates any remapping structure (updates to not-present or >> present entries). Those invalidation commands are used to trap and >> update host structures. This mode was devised for virtualization. I was >> not able to find such "caching mode" on ARM SMMU. Is there any? >> >> If not, do you have any other suggestion, I mean, besides the >> virtio-based solution. >> >> Thanks >> >> Eric > > Does SMMU hardware have nested page table support? > Some IOMMUs have this. Sorry for the delay. Yes it has and was supposed to serve that use case; but using the feature was not advised as far as I understand. Thanks Eric > > If yes then for some workloads this has the potential to perform better > than the invalidation hack with host SMMU performing nested translations > using guest page tables. >
