The host might miss APIC timer interrupts if the guest enters a specific
C-state. Quoting the erratum:
400 APIC Timer Interrupt Does Not Occur in Processor C-States
Description
An APIC timer interrupt that becomes pending in low-power states C1E
or C3 will not cause the processor to enter the C0 state even if the
interrupt is enabled by Timer Local Vector Table Entry[Mask],
APIC320[16]). APIC timer functionality is otherwise unaffected.
Potential Effect on System
System hang may occur provided that the operating system has not
configured another interrupt source. APIC timer interrupts may be
delayed or, when the APIC timer is configured in rollover mode
(APIC320[17]), the APIC timer may roll over multiple times in the
low-power state with only one interrupt presented after the processor
resumes. The standard use of the APIC timer does not make this effect
significant.
Signed-off-by: Radim Krčmář <rkrcmar@xxxxxxxxxx>
---
arch/x86/kvm/x86.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h
index 612067074905..3ed7dd8737ab 100644
--- a/arch/x86/kvm/x86.h
+++ b/arch/x86/kvm/x86.h
@@ -223,8 +223,7 @@ static inline bool kvm_mwait_in_guest(void)
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_AMD:
- /* All AMD CPUs have a working MWAIT implementation */
- return true;
+ return !boot_cpu_has_bug(X86_BUG_AMD_E400);
case X86_VENDOR_INTEL:
/* Handle Intel below */
break;
--
2.12.2
