On Tue, Apr 04, 2017 at 08:15:09PM +0200, Paolo Bonzini wrote:
>
>
> On 04/04/2017 19:57, Christoffer Dall wrote:
> >> Right. That code does
> >>
> >> tmp->arch.power_off = true;
> >> kvm_vcpu_kick(tmp);
> >>
> >> and I think what's really missing in arm.c is the "if (vcpu->mode ==
> >> EXITING_GUEST_MODE)" check that is found in x86.c. Then pausing can
> >> also simply use kvm_vcpu_kick.
> > I see, that's why the cmpxchg() works the way it does. We just still
> > need to move the vcpu->mode = IN_GUEST_MODE before our
> > with-interrupts-disabled check.
> >
> > What I'm not sure is why you can get away without using a memory barrier
> > or WRITE_ONCE on x86, but is this simply because x86 is a strongly
> > ordered architecture?
>
> x86 does have a memory barrier:
>
> vcpu->mode = IN_GUEST_MODE;
>
> srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
> smp_mb__after_srcu_read_unlock();
duh, the long complicated barrier version made me totally miss it.
Sorry.
>
> /*
> * This handles the case where a posted interrupt was
> * notified with kvm_vcpu_kick.
> */
> if (kvm_lapic_enabled(vcpu)) {
> if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
> kvm_x86_ops->sync_pir_to_irr(vcpu);
> }
>
> if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
>
> and WRITE_ONCE is not needed if you have a memory barrier (though I find it
> more self-documenting to use it anyway).
>
ok, thanks.
-Christoffer
