On 26/03/2017 23:51, Borislav Petkov wrote:
> From: Borislav Petkov <bp@xxxxxxx>
>
> MCG_CAP[63:9] bits are reserved on AMD. However, on an AMD guest, this
> MSR returns 0x100010a. More specifically, bit 24 is set, which is simply
> wrong. That bit is MCG_SER_P and is present only on Intel. Thus, clean
> up the reserved bits in order not to confuse guests.
>
> Signed-off-by: Borislav Petkov <bp@xxxxxxx>
> Cc: Joerg Roedel <joro@xxxxxxxxxx>
> Cc: Paolo Bonzini <pbonzini@xxxxxxxxxx>
> Cc: "Radim Krčmář" <rkrcmar@xxxxxxxxxx>
> ---
> arch/x86/kvm/svm.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> index c02b9af2056a..aba6100ebb8d 100644
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -5251,6 +5251,12 @@ static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
> avic_handle_ldr_update(vcpu);
> }
>
> +static void svm_setup_mce(struct kvm_vcpu *vcpu)
> +{
> + /* [63:9] are reserved. */
> + vcpu->arch.mcg_cap &= 0x1ff;
> +}
> +
> static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
> .cpu_has_kvm_support = has_svm,
> .disabled_by_bios = is_disabled,
> @@ -5362,6 +5368,7 @@ static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
> .pmu_ops = &amd_pmu_ops,
> .deliver_posted_interrupt = svm_deliver_avic_intr,
> .update_pi_irte = svm_update_pi_irte,
> + .setup_mce = svm_setup_mce,
> };
>
> static int __init svm_init(void)
>
Queued for 4.12, thanks.
Paolo
