On 9 December 2016 at 17:22, Christopher Covington <cov@xxxxxxxxxxxxxx> wrote:
> On 12/08/2016 12:05 PM, Andrew Jones wrote:
>> The TCG PMU is barely implemented for ARM and not at all implemented
>> for AArch64. Let's not bother running the TCG-only tests yet. We'll
>> likely move them to a new TCG-only unittests.cfg at some point before
>> re-enabling them too.
>
> ID_AA64DFR0_EL1 isn't implemented in TCG, which should be first fixed
> and then tested. I think and hope we're in agreement on that.
Hmm? We have
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
/* We mask out the PMUVer field, because we don't currently
* implement the PMU. Not advertising it prevents the guest
* from trying to use it and getting UNDEFs on registers we
* don't implement.
*/
.resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
which strongly suggests that we implement it... is that buggy somehow?
thanks
-- PMM
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