On 1 December 2016 at 12:19, Andre Przywara <andre.przywara@xxxxxxx> wrote: > Hi, > > On 01/12/16 12:02, Peter Maydell wrote: >> On 1 December 2016 at 11:28, Andre Przywara <andre.przywara@xxxxxxx> wrote: >>> I don't think so. At least here as a _variable_ type uint32_t is >>> probably the right one, as the ARMv8 ARM explicitly says that PMCR is a >>> 32-bit register, for both bitnesses. >> >> For 64-bit ARM this is strictly speaking just shorthand for "64-bit >> register with the top 32-bit being RES0". It is in theory possible that >> a future architecture extension might define uses for those RES0 >> bits. > > I trade: "in theory possible that a future architecture extension might" > (that's four speculative terms, right?) against: > > ARMv8 ARM, D7.4.7 PMCR_EL0, Performance Monitors Control Register: > Attributes > PMCR_EL0 is a 32-bit register. As I say, this just means "64 bit with 32 RES0 bits". See DDI0487A.k C5.1.1 "System register width": # In AArch64 state, each encoding in the System instruction space can # provide access to a 64-bit register. An AArch64 System register is # described as either a 32-bit register or a 64-bit register. For # a 32-bit register, the upper bits, bits[63:32], are RES0. (ie the register is 64-bits, it's just "described as" 32-bits for convenience.) thanks -- PMM -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
