2016-11-04 15:00-0700, Jim Mattson:
> From the Intel SDM, volume 3, section 10.4.3, "Enabling or Disabling the
> Local APIC,"
>
> When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent
> to an IA-32 processor without an on-chip APIC. The CPUID feature flag
> for the APIC (see Section 10.4.2, "Presence of the Local APIC") is
> also set to 0.
>
> Signed-off-by: Jim Mattson <jmattson@xxxxxxxxxx>
> Reviewed-by: Ben Serebrin <serebrin@xxxxxxxxxx>
> Reviewed-by: David Matlack <dmatlack@xxxxxxxxxx>
> ---
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> @@ -81,7 +81,10 @@ int kvm_update_cpuid(struct kvm_vcpu *vcpu)
> best->ecx |= F(OSXSAVE);
> }
>
> + best->edx &= ~F(APIC);
This might prevent userspace LAPIC from working.
(The bit will always be zero.)
> if (apic) {
> + if (vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)
> + best->edx |= F(APIC);
vcpu->arch.apic_base should be correct regardless of lapic_in_kernel().
Userspace can update CPUID when it changes MSR_IA32_APICBASE_ENABLE, so
not handling CPUID update in KVM is fine, but KVM must not touch the
CPUID bit in that case.
> if (best->ecx & F(TSC_DEADLINE_TIMER))
> apic->lapic_timer.timer_mode_mask = 3 << 17;
> else
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