This series is adding simplest test cases for VT-d.
The series contains some conflict with Alex's PCI framework
enhancement, so I am marking it as RFC, I can rebase to Alex's work
after it's merged. Besides the conflict, the codes is workable, and
passed smoke test.
Currently only a very small test scope is covered:
* VT-d init
* DMAR: 4 bytes copy
* IR: MSI
However this series could be a base point to add more test cases for
VT-d. The problem is, there are many IOMMU error conditions which are
very hard to be triggered in a real guest (IOMMU has merely no
interface for guest user, and it's totally running in the background).
This piece of work can be a start point if we want to do more
complicated things and play around with Intel IOMMU devices (also for
IOMMU regression tests).
Please review. Thanks,
=================
To run the test:
./x86/run ./x86/intel-iommu.flat \
-M q35,kernel-irqchip=split -global ioapic.version=0x20 \
-device intel-iommu,intremap=on -device edu
Sample output:
pxdev:kvm-unit-tests [new-iommu-ut]# ./iommu_run.sh
/root/git/qemu/bin/x86_64-softmmu/qemu-system-x86_64 -enable-kvm -device pc-testdev -device isa-debug-exit,iobase=0xf4,iosize=0x4 -vnc none -serial stdio -device pci-testdev -kernel ./x86/intel-iommu.flat -M q35,kernel-irqchip=split -global ioapic.version=0x20 -device intel-iommu,intremap=on -device edu
enabling apic
paging enabled
cr0 = 80010011
cr3 = 7fff000
cr4 = 20
VT-d version: 0x10
cap: 0x0012008c22260206
ecap: 0x0000000000f00f1a
PASS: init status check
PASS: fault status check
PASS: QI enablement
DMAR table address: 0x0000000007ff9000
PASS: DMAR table setup
IR table address: 0x0000000007ff8000
PASS: IR table setup
PASS: DMAR enablement
PASS: IR enablement
PASS: DMAR support 39 bits address width
PASS: DMAR support huge pages
PCI: init dev 0x0020 BAR 0 [MEM] addr 0xfea00000
PCI detected cap 0x5
Detected MSI for device 0x20 offset 0x40
allocated vt-d root entry for PCI bus 0
allocated vt-d context entry for devfn 0x20
map 4K page IOVA 0x0 to 0x7ff7000 (sid=0x0020)
edu device DMA start TO addr 0x0 size 0x4 off 0x0
edu device DMA start FROM addr 0x4 size 0x4 off 0x0
PASS: DMAR 4B memcpy test
INTR: setup IRTE index 0
MSI: dev 0x20 init 64bit address: addr=0xfee00010, data=0x0
PASS: EDU factorial INTR test
SUMMARY: 11 tests
=================
Peter Xu (14):
x86: vm: allow multiple init for vm setup
x86: smp: allow multiple init for smp setup
x86: intel-iommu: add vt-d init test
pci: refactor init process to pci_dev_init()
page: add page alignment checker
util: move MAX/MIN macro into util.h
vm/page: provide PGDIR_OFFSET() macro
x86: pci: add pci_config_{read|write}[bw]() helpers
pci: provide pci_set_master()
pci: add bdf helpers
pci: edu: introduce pci-edu helpers
x86: intel-iommu: add dmar test
pci: add msi support for 32/64bit address
x86: intel-iommu: add IR test
lib/alloc.c | 3 -
lib/asm-generic/page.h | 5 +
lib/pci-edu.c | 140 +++++++++++++++++++
lib/pci-edu.h | 36 +++++
lib/pci.c | 143 +++++++++++++++----
lib/pci.h | 37 ++++-
lib/util.h | 3 +
lib/x86/asm/page.h | 3 +
lib/x86/asm/pci.h | 37 ++++-
lib/x86/intel-iommu.c | 363 +++++++++++++++++++++++++++++++++++++++++++++++++
lib/x86/intel-iommu.h | 130 ++++++++++++++++++
lib/x86/smp.c | 6 +
lib/x86/vm.c | 11 +-
x86/Makefile.common | 1 +
x86/Makefile.x86_64 | 2 +
x86/intel-iommu.c | 138 +++++++++++++++++++
x86/vmexit.c | 22 +--
17 files changed, 1026 insertions(+), 54 deletions(-)
create mode 100644 lib/pci-edu.c
create mode 100644 lib/pci-edu.h
create mode 100644 lib/x86/intel-iommu.c
create mode 100644 lib/x86/intel-iommu.h
create mode 100644 x86/intel-iommu.c
--
2.7.4
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