[kvm-unit-tests PATCH] x86: move APIC timer related defines to headers

[Radim Krčmář <rkrcmar@xxxxxxxxxx>]

Change names to match Linux where necessary.

Signed-off-by: Radim Krčmář <rkrcmar@xxxxxxxxxx>
---
 Applies after Peter's "x86: apic: add LVTT test"

 lib/x86/apic-defs.h       | 2 ++
 lib/x86/msr.h             | 1 +
 x86/apic.c                | 8 ++------
 x86/tscdeadline_latency.c | 5 +----
 4 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/lib/x86/apic-defs.h b/lib/x86/apic-defs.h
index 94112b4b48f9..e0c3ccacfd4e 100644
--- a/lib/x86/apic-defs.h
+++ b/lib/x86/apic-defs.h
@@ -91,7 +91,9 @@
 #define		APIC_TIMER_BASE_CLKIN		0x0
 #define		APIC_TIMER_BASE_TMBASE		0x1
 #define		APIC_TIMER_BASE_DIV		0x2
+#define		APIC_LVT_TIMER_ONESHOT		(0 << 17)
 #define		APIC_LVT_TIMER_PERIODIC		(1 << 17)
+#define		APIC_LVT_TIMER_TSCDEADLINE	(2 << 17)
 #define		APIC_LVT_MASKED			(1 << 16)
 #define		APIC_LVT_LEVEL_TRIGGER		(1 << 15)
 #define		APIC_LVT_REMOTE_IRR		(1 << 14)
diff --git a/lib/x86/msr.h b/lib/x86/msr.h
index 281255acecae..2c0598c620b0 100644
--- a/lib/x86/msr.h
+++ b/lib/x86/msr.h
@@ -401,6 +401,7 @@
 #define MSR_IA32_VMX_TRUE_EXIT		0x0000048f
 #define MSR_IA32_VMX_TRUE_ENTRY		0x00000490
 
+#define MSR_IA32_TSCDEADLINE		0x000006e0
 
 /* AMD-V MSRs */
 
diff --git a/x86/apic.c b/x86/apic.c
index 4dc7a7b1480f..fefb584cfedf 100644
--- a/x86/apic.c
+++ b/x86/apic.c
@@ -15,10 +15,7 @@ static void test_lapic_existence(void)
     report("apic existence", (u16)lvr == 0x14);
 }
 
-#define TSC_DEADLINE_TIMER_MODE (2 << 17)
 #define TSC_DEADLINE_TIMER_VECTOR 0xef
-#define MSR_IA32_TSC            0x00000010
-#define MSR_IA32_TSCDEADLINE    0x000006e0
 
 static int tdt_count;
 
@@ -44,7 +41,7 @@ static int enable_tsc_deadline_timer(void)
     uint32_t lvtt;
 
     if (cpuid(1).c & (1 << 24)) {
-        lvtt = TSC_DEADLINE_TIMER_MODE | TSC_DEADLINE_TIMER_VECTOR;
+        lvtt = APIC_LVT_TIMER_TSCDEADLINE | TSC_DEADLINE_TIMER_VECTOR;
         apic_write(APIC_LVTT, lvtt);
         return 1;
     } else {
@@ -365,13 +362,12 @@ static void test_apic_timer_one_shot(void)
     static const uint32_t interval = 0x10000;
 
 #define APIC_LVT_TIMER_VECTOR    (0xee)
-#define APIC_LVT_TIMER_ONE_SHOT  (0)
 
     handle_irq(APIC_LVT_TIMER_VECTOR, lvtt_handler);
     irq_enable();
 
     /* One shot mode */
-    apic_write(APIC_LVTT, APIC_LVT_TIMER_ONE_SHOT |
+    apic_write(APIC_LVTT, APIC_LVT_TIMER_ONESHOT |
                APIC_LVT_TIMER_VECTOR);
     /* Divider == 1 */
     apic_write(APIC_TDCR, 0x0000000b);
diff --git a/x86/tscdeadline_latency.c b/x86/tscdeadline_latency.c
index 48cb0f16ec53..0592802257c6 100644
--- a/x86/tscdeadline_latency.c
+++ b/x86/tscdeadline_latency.c
@@ -37,10 +37,7 @@ static void test_lapic_existence(void)
     report("apic existence", (u16)lvr == 0x14);
 }
 
-#define TSC_DEADLINE_TIMER_MODE (2 << 17)
 #define TSC_DEADLINE_TIMER_VECTOR 0xef
-#define MSR_IA32_TSC            0x00000010
-#define MSR_IA32_TSCDEADLINE    0x000006e0
 
 static int tdt_count;
 u64 exptime;
@@ -84,7 +81,7 @@ static int enable_tsc_deadline_timer(void)
     uint32_t lvtt;
 
     if (cpuid(1).c & (1 << 24)) {
-        lvtt = TSC_DEADLINE_TIMER_MODE | TSC_DEADLINE_TIMER_VECTOR;
+        lvtt = APIC_LVT_TIMER_TSCDEADLINE | TSC_DEADLINE_TIMER_VECTOR;
         apic_write(APIC_LVTT, lvtt);
         start_tsc_deadline_timer();
         return 1;
-- 
2.10.0

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