On 07/08/16 14:01, Paolo Bonzini wrote:
> Reported-by: Laszlo Ersek <lersek@xxxxxxxxxx>
> Signed-off-by: Paolo Bonzini <pbonzini@xxxxxxxxxx>
> ---
> arch/x86/kvm/x86.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 388d9ffd7551..c01b0b3a06aa 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -7494,6 +7494,7 @@ void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
> if (!init_event) {
> kvm_pmu_reset(vcpu);
> vcpu->arch.smbase = 0x30000;
> + vcpu->arch.msr_ia32_feature_control = 0;
> }
>
> memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
> --
> 1.8.3.1
>
Actually I'm not sure whether zeroing MSR_IA32_FEATURE_CONTROL on
reset is the accurate behavior.
I know as Laszlo reported that Intel SDM says
VMXON is also controlled by the IA32_FEATURE_CONTROL MSR (MSR
address 3AH). This MSR is *cleared to zero* when a logical processor
is reset
However, when the later section "ARCHITECTURAL MSRS" in Chapter
"MODEL-SPECIFIC REGISTERS (MSRS)" explains the Lock bit of
MSR_IA32_FEATURE_CONTROL in Table "IA-32 Architectural MSRs", it says
... once the Lock bit is set, the entire IA32_FEATURE_CONTROL
contents are *preserved* across RESET when PWRGOOD is not
deasserted.
This looks like a conflict. I'm asking my Intel colleagues for the
accurate behavior.
Thanks,
Haozhong
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