On 06/07/2016 12:29, Wanpeng Li wrote:
> BUG: unable to handle kernel NULL pointer dereference at (null)
> IP: [< (null)>] (null)
> PGD 0
> Oops: 0010 [#1] SMP
> Call Trace:
> ? kvm_lapic_expired_hv_timer+0x47/0x90 [kvm]
> handle_preemption_timer+0xe/0x20 [kvm_intel]
> vmx_handle_exit+0x169/0x15a0 [kvm_intel]
> ? kvm_arch_vcpu_ioctl_run+0xd5d/0x19d0 [kvm]
> kvm_arch_vcpu_ioctl_run+0xdee/0x19d0 [kvm]
> ? kvm_arch_vcpu_ioctl_run+0xd5d/0x19d0 [kvm]
> ? vcpu_load+0x1c/0x60 [kvm]
> ? kvm_arch_vcpu_load+0x57/0x260 [kvm]
> kvm_vcpu_ioctl+0x2d3/0x7c0 [kvm]
> do_vfs_ioctl+0x96/0x6a0
> ? __fget_light+0x2a/0x90
> SyS_ioctl+0x79/0x90
> do_syscall_64+0x68/0x180
> entry_SYSCALL64_slow_path+0x25/0x25
> Code: Bad RIP value.
> RIP [< (null)>] (null)
> RSP <ffff8800b5263c48>
> CR2: 0000000000000000
> ---[ end trace 9c70c48b1a2bc66e ]---
This is happening in L2, while the patch is for L1, right? So the commit
title should be "KVM: nVMX: fix incorrect preemption timer vmexit in nested guest".
The patch looks correct, but I'm not sure how you get a preemption
timer vmexit while vmcs02 is active:
exec_control = vmcs12->pin_based_vm_exec_control;
exec_control |= vmcs_config.pin_based_exec_ctrl;
exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
In other words, don't you need something like
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index f6e5cc679898..edf925a2da9d 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -1121,9 +1121,6 @@ static inline bool cpu_has_broken_vmx_preemption_timer(void)
static inline bool cpu_has_vmx_preemption_timer(void)
{
- if (cpu_has_broken_vmx_preemption_timer())
- return false;
-
return vmcs_config.pin_based_exec_ctrl &
PIN_BASED_VMX_PREEMPTION_TIMER;
}
@@ -3406,6 +3403,9 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
&_pin_based_exec_control) < 0)
return -EIO;
+
+ if (cpu_has_broken_vmx_preemption_timer())
+ _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
if (!(_cpu_based_2nd_exec_control &
SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
@@ -9797,8 +9796,10 @@ static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
vmcs_write64(VMCS_LINK_POINTER, -1ull);
exec_control = vmcs12->pin_based_vm_exec_control;
+ exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
exec_control |= vmcs_config.pin_based_exec_ctrl;
- exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
+ if (vmx->hv_deadline_tsc == -1)
+ exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
if (nested_cpu_has_posted_intr(vmcs12)) {
/*
for the L1 TSC deadline timer to trigger while L2 is running? It's untested,
but this would replace the patch that Haozhong submitted earlier.
Paolo
> Cc: Paolo Bonzini <pbonzini@xxxxxxxxxx>
> Cc: Radim Krčmář <rkrcmar@xxxxxxxxxx>
> Cc: Yunhong Jiang <yunhong.jiang@xxxxxxxxx>
> Cc: Jan Kiszka <jan.kiszka@xxxxxxxxxxx>
> Cc: Haozhong Zhang <haozhong.zhang@xxxxxxxxx>
> Signed-off-by: Wanpeng Li <wanpeng.li@xxxxxxxxxxx>
> ---
> v1 -> v2:
> * fix typo in patch description
>
> arch/x86/kvm/vmx.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> index 85e2f0a..29c16a8 100644
> --- a/arch/x86/kvm/vmx.c
> +++ b/arch/x86/kvm/vmx.c
> @@ -8041,6 +8041,8 @@ static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
> return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
> case EXIT_REASON_PCOMMIT:
> return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
> + case EXIT_REASON_PREEMPTION_TIMER:
> + return false;
> default:
> return true;
> }
>
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