Re: [PATCH V4 4/4] Utilize the vmx preemption timer for tsc deadline timer

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2016-06-14 5:20 GMT+08:00 Yunhong Jiang <yunhong.jiang@xxxxxxxxxxxxxxx>:
[...]
> +
> +void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
> +{
> +       struct kvm_lapic *apic = vcpu->arch.apic;
> +
> +       /* Possibly the TSC deadline timer is not enabled yet */
> +       if (!apic->lapic_timer.hv_timer_in_use)
> +               return;
> +
> +       kvm_x86_ops->cancel_hv_timer(vcpu);
> +       apic->lapic_timer.hv_timer_in_use = false;
> +
> +       if (atomic_read(&apic->lapic_timer.pending))
> +               return;
> +
> +       start_sw_tscdeadline(apic);

I have one question here. For example, tsc deadline is set to 10us in
kvm_set_lapic_tscdeadline_msr(), and 1us past in preemption timer,
then 9us should be set to hrtimer expire during switch to sw timer,
however, apic->lapic_timer.tscdeadline is still 10us, so the current
codes set 10us to hrtimer expire. Where I miss?

Regards,
Wanpeng Li
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