Changes in v5: * v4 Patch 1&2 are now merged into v5 Patch 1. (Paolo Bonzini) * Add a separate Patch 3 to automatically enable LMCE for "-cpu host" if host does support. (Eduardo Habkost) * Move the sanity check of misconfiguration of LMCE to a separate Patch 4. I'm fine to drop it if it's considered to be unnecessary. (Eduardo Habkost) * Move check of MCG_LMCE_P capability to the existing code in kvm_arch_init_vcpu(). The difference is that if LMCE is not supported by host but MCG_LMCE_P is included in env->mcg_cap, kvm_arch_init_vcpu() return with error instead of just reporting a warning. (Eduardo Habkost) * Fix setting has_msr_feature_control in kvm_arch_init_vcpu(). (Paolo Bonzini) * Fix the type error in fw_cfg file "etc/msr_feature_control". Changes in v4: * Abort starting QEMU if lmce option is present but host does support LMCE. (Eduardo Habkost) * Remove setting MSR_IA32_FEATURE_CONTROL, which should be left to guest. (Radim Krčmá, Paolo Bonzini * Adjust error messages in mce_init(). (Boris Petkov) * Move adding option 'lmce' to patch 1. (Eduardo Habkost, Paolo Bonzini) * Adjust LMCE error message in cpu_post_load(). (Eduardo Habkost) * (Patch 3) Add a fw_cfg file 'etc/msr_feature_control' to advise bits should be set in MSR_IA32_FEATURE_CONTROL. (Paolo Bonzini) * Fix SOB chain in patch 1. Changes in v3: * LMCE can be enabled only for non-intel guests. * LMCE is disabled by default and a cpu option 'lmce=on/off' is added to explicitly enable/disable LMCE. * LMCE is disabled if KVM does not support (even though 'lmce=on'). * VM on LMCE-enabled QEMU can be only migrated to LMCE-enabled QEMU. * MCG_LMCE_P is not included in MCE_CAP_DEF and instead added to env->mcg_cap if LMCE is enabled. * Code style fix. This QEMU patch series along with the corresponding KVM patch series (sent via another email with title "[PATCH v3 0/3] Add KVM support for Intel local MCE") enables Intel local MCE feature for guest. Intel Local MCE (LMCE) is a feature on Intel Skylake Server CPU that can deliver MCE to a single processor thread instead of broadcasting to all threads, which can reduce software's load when processing MCE on machines with a large number of processor threads. The technical details of LMCE can be found in Intel SDM Vol 3, Chapter "Machine-Check Architecture" (search for 'LMCE'). Basically, * The capability of LMCE is indicated by bit 27 (MCG_LMCE_P) of MSR_IA32_MCG_CAP. * LMCE is enabled by setting bit 20 (MSR_IA32_FEATURE_CONTROL_LMCE) of MSR_IA32_FEATURE_CONTROL and bit 0 (MCG_EXT_CTL_LMCE_EN) of MSR_IA32_MCG_EXT_CTL. * Software can determine if a MCE is local to the current processor thread by checking bit 2 (MCG_STATUS_LMCE) of MSR_IA32_MCG_STATUS. Ashok Raj (1): target-i386: KVM: add basic Intel LMCE support Haozhong Zhang (3): i386: publish advised value of MSR_IA32_FEATURE_CONTROL via fw_cfg target-i386: enable LMCE for '-cpu host' if supported by host target-i386: abort migration if LMCE config mismatch hw/i386/pc.c | 29 +++++++++++++++++++++++++++++ target-i386/cpu.c | 19 ++++++++++++++++++- target-i386/cpu.h | 16 ++++++++++++++++ target-i386/kvm.c | 36 +++++++++++++++++++++++++++++++++--- target-i386/machine.c | 25 +++++++++++++++++++++++++ 5 files changed, 121 insertions(+), 4 deletions(-) -- 2.9.0 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
