On 05/06/2016 17:41, Haozhong Zhang wrote:
> On 06/04/16 12:34, Boris Petkov wrote:
>> Haozhong Zhang <haozhong.zhang@xxxxxxxxx> wrote:
>>
>>> This patch adds the support to inject SRAR and SRAO as LMCE, i.e. they
>>> will be injected to only one VCPU rather than broadcast to all
>>> VCPUs. As KVM reports LMCE support on Intel platforms, this features is
>>> only available on Intel platforms.
>>>
>>> Signed-off-by: Ashok Raj <ashok.raj@xxxxxxxxx>
>>> Signed-off-by: Haozhong Zhang <haozhong.zhang@xxxxxxxxx>
>>> ---
>>> Cc: Paolo Bonzini <pbonzini@xxxxxxxxxx>
>>> Cc: Richard Henderson <rth@xxxxxxxxxxx>
>>> Cc: Eduardo Habkost <ehabkost@xxxxxxxxxx>
>>> Cc: Marcelo Tosatti <mtosatti@xxxxxxxxxx>
>>> Cc: Boris Petkov <bp@xxxxxxx>
>>> Cc: kvm@xxxxxxxxxxxxxxx
>>> Cc: Tony Luck <tony.luck@xxxxxxxxx>
>>> Cc: Andi Kleen <andi.kleen@xxxxxxxxx>
>>> ---
>>> target-i386/cpu.c | 26 ++++++++++++++++++++++++++
>>> target-i386/cpu.h | 13 ++++++++++++-
>>> target-i386/kvm.c | 35 +++++++++++++++++++++++++++++++----
>>> 3 files changed, 69 insertions(+), 5 deletions(-)
>>
>> ...
>>
>>> @@ -1173,6 +1182,8 @@ struct X86CPU {
>>> */
>>> bool enable_pmu;
>>>
>>> + bool enable_lmce;
>>
>> That struct would go fat pretty fast if it grows a bool per CPU feature. Perhaps a more clever, a-bit-per-featurebit scheme would be in order.
>
> OK, I'll use a 64-bit integer for current and future features.
No, please keep this as is for now. It can be refactored later.
Paolo
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