On Wed, Apr 27, 2016 at 04:13:06PM +0800, Xiao Guangrong wrote:
> From: Eduardo Habkost <ehabkost@xxxxxxxxxx>
>
> Introduce Skylake-Client cpu mode which inherits the features from
> Broadwell and supports some additional features that are: MPX,
> XSAVEC, XSAVES and XGETBV1
>
> Note:
> 1. As XSAVES is disabled in upstream linux kernel by commit e88221c50
> (x86/fpu: Disable XSAVES* support for now), QEMU will complain about
> "warning: host doesn't support requested feature: CPUID.0DH:EAX.xsaves [bit 3]"
Seeing this warning means live migration will be broken (maybe we
should mention this explicitly in the warning output). If XSAVES
is still not supported, we shouldn't add it yet. I see 2 options:
1) Add a CPU model without XSAVES today (e.g.
"Skylake-Client-noXSAVES"), and add a new one with XSAVES
("Skylake-Client") once we have XSAVES working on some hosts.
Then both cases would be supported out of the box.
2) Wait until we have XSAVES working, and only add a CPU model
with XSAVES. This means -cpu Skylake-Client would work out of
the box only on hosts with XSAVES. Older systems would require
using an older CPU model (e.g. Broadwell) or "-cpu
Skylake-Client,-XSAVES".
I guess it depends on how long we expect to take for XSAVES
support to become available. If it won't take long, we can do
(2). If it will take a few kernel releases, we could do (1).
We've already had at least 5 kernel releases without XSAVES
support (v4.1 to v4.6-rc5), so I believe we should do (1).
What do others think?
>
> 2. We will post out the patch introducing Skylake-Server mode once it
> has been verified on a Skylake Sever machine
Thanks!
>
> [ Xiao: largely based on Eduardo's work, introduce Skylake-Client and
> Skylake-Server cpu modes separately. ]
>
> Signed-off-by: Eduardo Habkost <ehabkost@xxxxxxxxxx>
> Signed-off-by: Xiao Guangrong <guangrong.xiao@xxxxxxxxxxxxxxx>
> ---
> target-i386/cpu.c | 39 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index ddae932..2f2c647 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -1228,6 +1228,45 @@ static X86CPUDefinition builtin_x86_defs[] = {
> .model_id = "Intel Core Processor (Broadwell)",
> },
> {
> + .name = "Skylake-Client",
> + .level = 0xd,
> + .vendor = CPUID_VENDOR_INTEL,
> + .family = 6,
> + .model = 94,
> + .stepping = 3,
> + .features[FEAT_1_EDX] =
> + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
> + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
> + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
> + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> + CPUID_DE | CPUID_FP87,
> + .features[FEAT_1_ECX] =
> + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
> + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
> + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
> + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
> + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
> + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
> + .features[FEAT_8000_0001_EDX] =
> + CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
> + CPUID_EXT2_SYSCALL,
> + .features[FEAT_8000_0001_ECX] =
> + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
> + .features[FEAT_7_0_EBX] =
> + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
> + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
> + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
> + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
> + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
> + .features[FEAT_XSAVE] =
> + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XSAVES |
> + CPUID_XSAVE_XGETBV1,
> + .features[FEAT_6_EAX] =
> + CPUID_6_EAX_ARAT,
> + .xlevel = 0x80000008,
> + .model_id = "Intel Core Processor (Skylake)",
> + },
> + {
> .name = "Opteron_G1",
> .level = 5,
> .vendor = CPUID_VENDOR_AMD,
> --
> 1.8.3.1
>
--
Eduardo
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