Re: [PART1 RFC v3 01/12] KVM: x86: Misc LAPIC changes to expose helper functions

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On 18/03/2016 07:09, Suravee Suthikulpanit wrote:
> From: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>
> 
> Exporting LAPIC utility functions and macros for re-use in SVM code.
> 
> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>
> ---
>  arch/x86/kvm/lapic.c | 110 ++++++++++++++++++++++++++-------------------------
>  arch/x86/kvm/lapic.h |   8 ++++
>  2 files changed, 65 insertions(+), 53 deletions(-)
> 
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 3a045f3..6da1628 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -59,9 +59,8 @@
>  /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
>  #define apic_debug(fmt, arg...)
>  
> -#define APIC_LVT_NUM			6
>  /* 14 is the version for Xeon and Pentium 8.4.8*/
> -#define APIC_VERSION			(0x14UL | ((APIC_LVT_NUM - 1) << 16))
> +#define APIC_VERSION			(0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
>  #define LAPIC_MMIO_LENGTH		(1 << 12)
>  /* followed define is not in apicdef.h */
>  #define APIC_SHORT_MASK			0xc0000
> @@ -76,10 +75,11 @@
>  #define VEC_POS(v) ((v) & (32 - 1))
>  #define REG_POS(v) (((v) >> 5) << 4)
>  
> -static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
> +void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
>  {
>  	*((u32 *) (apic->regs + reg_off)) = val;
>  }
> +EXPORT_SYMBOL_GPL(kvm_lapic_set_reg);
>  
>  static inline int apic_test_vector(int vec, void *bitmap)
>  {

Please keep the function inline, moving it to lapic.h

> @@ -94,10 +94,11 @@ bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
>  		apic_test_vector(vector, apic->regs + APIC_IRR);
>  }
>  
> -static inline void apic_set_vector(int vec, void *bitmap)
> +void kvm_lapic_set_vector(int vec, void *bitmap)
>  {
>  	set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
>  }
> +EXPORT_SYMBOL_GPL(kvm_lapic_set_vector);

Same here, and also move apic_set_irr to lapic.h so that you don't have
to use the lower-level apic_set_vector directly.  (Of course renaming it
to kvm_lapic_set_irr).

Otherwise okay.

Paolo

>  static inline void apic_clear_vector(int vec, void *bitmap)
>  {
> @@ -212,7 +213,7 @@ static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
>  {
>  	bool enabled = val & APIC_SPIV_APIC_ENABLED;
>  
> -	apic_set_reg(apic, APIC_SPIV, val);
> +	kvm_lapic_set_reg(apic, APIC_SPIV, val);
>  
>  	if (enabled != apic->sw_enabled) {
>  		apic->sw_enabled = enabled;
> @@ -226,13 +227,13 @@ static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
>  
>  static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id)
>  {
> -	apic_set_reg(apic, APIC_ID, id << 24);
> +	kvm_lapic_set_reg(apic, APIC_ID, id << 24);
>  	recalculate_apic_map(apic->vcpu->kvm);
>  }
>  
>  static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
>  {
> -	apic_set_reg(apic, APIC_LDR, id);
> +	kvm_lapic_set_reg(apic, APIC_LDR, id);
>  	recalculate_apic_map(apic->vcpu->kvm);
>  }
>  
> @@ -240,8 +241,8 @@ static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id)
>  {
>  	u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
>  
> -	apic_set_reg(apic, APIC_ID, id << 24);
> -	apic_set_reg(apic, APIC_LDR, ldr);
> +	kvm_lapic_set_reg(apic, APIC_ID, id << 24);
> +	kvm_lapic_set_reg(apic, APIC_LDR, ldr);
>  	recalculate_apic_map(apic->vcpu->kvm);
>  }
>  
> @@ -287,10 +288,10 @@ void kvm_apic_set_version(struct kvm_vcpu *vcpu)
>  	feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
>  	if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
>  		v |= APIC_LVR_DIRECTED_EOI;
> -	apic_set_reg(apic, APIC_LVR, v);
> +	kvm_lapic_set_reg(apic, APIC_LVR, v);
>  }
>  
> -static const unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
> +static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
>  	LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
>  	LVT_MASK | APIC_MODE_MASK,	/* LVTTHMR */
>  	LVT_MASK | APIC_MODE_MASK,	/* LVTPC */
> @@ -351,7 +352,7 @@ EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
>  
>  static inline void apic_set_irr(int vec, struct kvm_lapic *apic)
>  {
> -	apic_set_vector(vec, apic->regs + APIC_IRR);
> +	kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
>  	/*
>  	 * irr_pending must be true if any interrupt is pending; set it after
>  	 * APIC_IRR to avoid race with apic_clear_irr
> @@ -569,7 +570,7 @@ static void apic_update_ppr(struct kvm_lapic *apic)
>  		   apic, ppr, isr, isrv);
>  
>  	if (old_ppr != ppr) {
> -		apic_set_reg(apic, APIC_PROCPRI, ppr);
> +		kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
>  		if (ppr < old_ppr)
>  			kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
>  	}
> @@ -577,7 +578,7 @@ static void apic_update_ppr(struct kvm_lapic *apic)
>  
>  static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
>  {
> -	apic_set_reg(apic, APIC_TASKPRI, tpr);
> +	kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
>  	apic_update_ppr(apic);
>  }
>  
> @@ -674,6 +675,7 @@ bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
>  		return false;
>  	}
>  }
> +EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
>  
>  bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
>  		struct kvm_lapic_irq *irq, int *r, unsigned long *dest_map)
> @@ -844,7 +846,7 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
>  
>  		if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
>  			if (trig_mode)
> -				apic_set_vector(vector, apic->regs + APIC_TMR);
> +				kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
>  			else
>  				apic_clear_vector(vector, apic->regs + APIC_TMR);
>  		}
> @@ -1109,7 +1111,7 @@ static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
>  	return container_of(dev, struct kvm_lapic, dev);
>  }
>  
> -static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
> +int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
>  		void *data)
>  {
>  	unsigned char alignment = offset & 0xf;
> @@ -1146,6 +1148,7 @@ static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
>  	}
>  	return 0;
>  }
> +EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
>  
>  static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
>  {
> @@ -1163,7 +1166,7 @@ static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
>  	if (!apic_mmio_in_range(apic, address))
>  		return -EOPNOTSUPP;
>  
> -	apic_reg_read(apic, offset, len, data);
> +	kvm_lapic_reg_read(apic, offset, len, data);
>  
>  	return 0;
>  }
> @@ -1348,7 +1351,7 @@ static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
>  	}
>  }
>  
> -static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
> +int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
>  {
>  	int ret = 0;
>  
> @@ -1380,7 +1383,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
>  
>  	case APIC_DFR:
>  		if (!apic_x2apic_mode(apic)) {
> -			apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
> +			kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
>  			recalculate_apic_map(apic->vcpu->kvm);
>  		} else
>  			ret = 1;
> @@ -1395,10 +1398,10 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
>  			int i;
>  			u32 lvt_val;
>  
> -			for (i = 0; i < APIC_LVT_NUM; i++) {
> +			for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
>  				lvt_val = kvm_apic_get_reg(apic,
>  						       APIC_LVTT + 0x10 * i);
> -				apic_set_reg(apic, APIC_LVTT + 0x10 * i,
> +				kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
>  					     lvt_val | APIC_LVT_MASKED);
>  			}
>  			apic_update_lvtt(apic);
> @@ -1409,14 +1412,14 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
>  	}
>  	case APIC_ICR:
>  		/* No delay here, so we always clear the pending bit */
> -		apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
> +		kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
>  		apic_send_ipi(apic);
>  		break;
>  
>  	case APIC_ICR2:
>  		if (!apic_x2apic_mode(apic))
>  			val &= 0xff000000;
> -		apic_set_reg(apic, APIC_ICR2, val);
> +		kvm_lapic_set_reg(apic, APIC_ICR2, val);
>  		break;
>  
>  	case APIC_LVT0:
> @@ -1430,7 +1433,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
>  			val |= APIC_LVT_MASKED;
>  
>  		val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
> -		apic_set_reg(apic, reg, val);
> +		kvm_lapic_set_reg(apic, reg, val);
>  
>  		break;
>  
> @@ -1438,7 +1441,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
>  		if (!kvm_apic_sw_enabled(apic))
>  			val |= APIC_LVT_MASKED;
>  		val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
> -		apic_set_reg(apic, APIC_LVTT, val);
> +		kvm_lapic_set_reg(apic, APIC_LVTT, val);
>  		apic_update_lvtt(apic);
>  		break;
>  
> @@ -1447,14 +1450,14 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
>  			break;
>  
>  		hrtimer_cancel(&apic->lapic_timer.timer);
> -		apic_set_reg(apic, APIC_TMICT, val);
> +		kvm_lapic_set_reg(apic, APIC_TMICT, val);
>  		start_apic_timer(apic);
>  		break;
>  
>  	case APIC_TDCR:
>  		if (val & 4)
>  			apic_debug("KVM_WRITE:TDCR %x\n", val);
> -		apic_set_reg(apic, APIC_TDCR, val);
> +		kvm_lapic_set_reg(apic, APIC_TDCR, val);
>  		update_divide_count(apic);
>  		break;
>  
> @@ -1467,7 +1470,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
>  
>  	case APIC_SELF_IPI:
>  		if (apic_x2apic_mode(apic)) {
> -			apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
> +			kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
>  		} else
>  			ret = 1;
>  		break;
> @@ -1479,6 +1482,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
>  		apic_debug("Local APIC Write to read-only register %x\n", reg);
>  	return ret;
>  }
> +EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
>  
>  static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
>  			    gpa_t address, int len, const void *data)
> @@ -1508,7 +1512,7 @@ static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
>  		apic_debug("%s: offset 0x%x with length 0x%x, and value is "
>  			   "0x%x\n", __func__, offset, len, val);
>  
> -	apic_reg_write(apic, offset & 0xff0, val);
> +	kvm_lapic_reg_write(apic, offset & 0xff0, val);
>  
>  	return 0;
>  }
> @@ -1516,7 +1520,7 @@ static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
>  void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
>  {
>  	if (kvm_vcpu_has_lapic(vcpu))
> -		apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
> +		kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
>  }
>  EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
>  
> @@ -1528,10 +1532,10 @@ void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
>  	/* hw has done the conditional check and inst decode */
>  	offset &= 0xff0;
>  
> -	apic_reg_read(vcpu->arch.apic, offset, 4, &val);
> +	kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
>  
>  	/* TODO: optimize to just emulate side effect w/o one more write */
> -	apic_reg_write(vcpu->arch.apic, offset, val);
> +	kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
>  }
>  EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
>  
> @@ -1670,28 +1674,28 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
>  		kvm_apic_set_id(apic, vcpu->vcpu_id);
>  	kvm_apic_set_version(apic->vcpu);
>  
> -	for (i = 0; i < APIC_LVT_NUM; i++)
> -		apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
> +	for (i = 0; i < KVM_APIC_LVT_NUM; i++)
> +		kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
>  	apic_update_lvtt(apic);
>  	if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
> -		apic_set_reg(apic, APIC_LVT0,
> +		kvm_lapic_set_reg(apic, APIC_LVT0,
>  			     SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
>  	apic_manage_nmi_watchdog(apic, kvm_apic_get_reg(apic, APIC_LVT0));
>  
> -	apic_set_reg(apic, APIC_DFR, 0xffffffffU);
> +	kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
>  	apic_set_spiv(apic, 0xff);
> -	apic_set_reg(apic, APIC_TASKPRI, 0);
> +	kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
>  	if (!apic_x2apic_mode(apic))
>  		kvm_apic_set_ldr(apic, 0);
> -	apic_set_reg(apic, APIC_ESR, 0);
> -	apic_set_reg(apic, APIC_ICR, 0);
> -	apic_set_reg(apic, APIC_ICR2, 0);
> -	apic_set_reg(apic, APIC_TDCR, 0);
> -	apic_set_reg(apic, APIC_TMICT, 0);
> +	kvm_lapic_set_reg(apic, APIC_ESR, 0);
> +	kvm_lapic_set_reg(apic, APIC_ICR, 0);
> +	kvm_lapic_set_reg(apic, APIC_ICR2, 0);
> +	kvm_lapic_set_reg(apic, APIC_TDCR, 0);
> +	kvm_lapic_set_reg(apic, APIC_TMICT, 0);
>  	for (i = 0; i < 8; i++) {
> -		apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
> -		apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
> -		apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
> +		kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
> +		kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
> +		kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
>  	}
>  	apic->irr_pending = vcpu->arch.apicv_active;
>  	apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
> @@ -2073,8 +2077,8 @@ int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
>  
>  	/* if this is ICR write vector before command */
>  	if (reg == APIC_ICR)
> -		apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
> -	return apic_reg_write(apic, reg, (u32)data);
> +		kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
> +	return kvm_lapic_reg_write(apic, reg, (u32)data);
>  }
>  
>  int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
> @@ -2091,10 +2095,10 @@ int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
>  		return 1;
>  	}
>  
> -	if (apic_reg_read(apic, reg, 4, &low))
> +	if (kvm_lapic_reg_read(apic, reg, 4, &low))
>  		return 1;
>  	if (reg == APIC_ICR)
> -		apic_reg_read(apic, APIC_ICR2, 4, &high);
> +		kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
>  
>  	*data = (((u64)high) << 32) | low;
>  
> @@ -2110,8 +2114,8 @@ int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
>  
>  	/* if this is ICR write vector before command */
>  	if (reg == APIC_ICR)
> -		apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
> -	return apic_reg_write(apic, reg, (u32)data);
> +		kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
> +	return kvm_lapic_reg_write(apic, reg, (u32)data);
>  }
>  
>  int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
> @@ -2122,10 +2126,10 @@ int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
>  	if (!kvm_vcpu_has_lapic(vcpu))
>  		return 1;
>  
> -	if (apic_reg_read(apic, reg, 4, &low))
> +	if (kvm_lapic_reg_read(apic, reg, 4, &low))
>  		return 1;
>  	if (reg == APIC_ICR)
> -		apic_reg_read(apic, APIC_ICR2, 4, &high);
> +		kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
>  
>  	*data = (((u64)high) << 32) | low;
>  
> diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
> index 41bdb35..7bf8184 100644
> --- a/arch/x86/kvm/lapic.h
> +++ b/arch/x86/kvm/lapic.h
> @@ -7,6 +7,7 @@
>  
>  #define KVM_APIC_INIT		0
>  #define KVM_APIC_SIPI		1
> +#define KVM_APIC_LVT_NUM	6
>  
>  struct kvm_timer {
>  	struct hrtimer timer;
> @@ -56,6 +57,12 @@ void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
>  void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
>  u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
>  void kvm_apic_set_version(struct kvm_vcpu *vcpu);
> +void kvm_lapic_set_vector(int vec, void *bitmap);
> +int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val);
> +int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
> +		       void *data);
> +bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
> +			   int short_hand, unsigned int dest, int dest_mode);
>  
>  void __kvm_apic_update_irr(u32 *pir, void *regs);
>  void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir);
> @@ -96,6 +103,7 @@ static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
>  int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data);
>  void kvm_lapic_init(void);
>  
> +void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val);
>  static inline u32 kvm_apic_get_reg(struct kvm_lapic *apic, int reg_off)
>  {
>  	        return *((u32 *) (apic->regs + reg_off));
> 
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