On 03/03/2016 02:09, Peter Feiner wrote:
> With optimizations disabled, the compiler generated a call for
> irq_enable() -- rather than just inlining an sti instruction as
> expected. Thus the irq_enable ret would run in the sti shadow and the
> vectors would fire in the wrong order.
>
> Signed-off-by: Peter Feiner <pfeiner@xxxxxxxxxx>
> ---
> x86/eventinj.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/x86/eventinj.c b/x86/eventinj.c
> index bddedce..202ac19 100644
> --- a/x86/eventinj.c
> +++ b/x86/eventinj.c
> @@ -296,8 +296,7 @@ int main()
> apic_self_ipi(32);
> flush_stack();
> io_delay();
> - irq_enable();
> - asm volatile ("int $33");
> + asm volatile ("sti; int $33");
> irq_disable();
> printf("After vec 32 and int $33\n");
> report("vec 32/int $33", test_count == 2);
>
I've added a comment to irq_enable too:
/* Note that irq_enable() does not ensure an interrupt shadow due
* to the vagaries of compiler optimizations. If you need the
* shadow, use a single asm with "sti" and the instruction after it.
*/
Paolo
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