As Igor suggested that we can report the BIOS patched operation region
so that OSPM could see that particular range is in use and be able to
notice conflicts if it happens some day
Signed-off-by: Xiao Guangrong <guangrong.xiao@xxxxxxxxxxxxxxx>
---
hw/acpi/nvdimm.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c
index e0b483a..a6359cc 100644
--- a/hw/acpi/nvdimm.c
+++ b/hw/acpi/nvdimm.c
@@ -566,6 +566,7 @@ static void nvdimm_build_ssdt(GSList *device_list, GArray *table_offsets,
GArray *table_data, GArray *linker)
{
Aml *ssdt, *sb_scope, *dev, *field;
+ Aml *min_addr, *max_addr, *mr32, *method, *crs;
int mem_addr_offset, nvdimm_ssdt;
acpi_add_table(table_offsets, table_data);
@@ -590,6 +591,32 @@ static void nvdimm_build_ssdt(GSList *device_list, GArray *table_offsets,
*/
aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0012")));
+ /*
+ * report the dsm memory so that OSPM could see that particular range is
+ * in use and be able to notice conflicts if it happens some day.
+ */
+ method = aml_method("_CRS", 0, AML_SERIALIZED);
+ crs = aml_resource_template();
+ aml_append(crs, aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
+ AML_MAX_FIXED, AML_CACHEABLE,
+ AML_READ_WRITE,
+ 0, 0x0, 0xFFFFFFFE, 0,
+ TARGET_PAGE_SIZE));
+ aml_append(method, aml_name_decl("MR32", crs));
+ mr32 = aml_name("MR32");
+ aml_append(method, aml_create_dword_field(mr32, aml_int(10), "MIN"));
+ aml_append(method, aml_create_dword_field(mr32, aml_int(14), "MAX"));
+
+ min_addr = aml_name("MIN");
+ max_addr = aml_name("MAX");
+
+ aml_append(method, aml_store(aml_name(NVDIMM_ACPI_MEM_ADDR), min_addr));
+ aml_append(method, aml_add(min_addr, aml_int(TARGET_PAGE_SIZE),
+ max_addr));
+ aml_append(method, aml_decrement(max_addr));
+ aml_append(method, aml_return(mr32));
+ aml_append(dev, method);
+
/* map DSM memory and IO into ACPI namespace. */
aml_append(dev, aml_operation_region("NPIO", AML_SYSTEM_IO,
aml_int(NVDIMM_ACPI_IO_BASE), NVDIMM_ACPI_IO_LEN));
--
1.8.3.1
--
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