On 08/12/15 12:47, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@xxxxxxxxxx>
>
> Add access handler which emulates writing and reading PMEVTYPERn or
> PMCCFILTR register. When writing to PMEVTYPERn or PMCCFILTR, call
> kvm_pmu_set_counter_event_type to create a perf_event for the selected
> event type.
>
> Signed-off-by: Shannon Zhao <shannon.zhao@xxxxxxxxxx>
> ---
> arch/arm64/kvm/sys_regs.c | 98 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 98 insertions(+)
>
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 1bcb2b7..2d8bd15 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -474,6 +474,12 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
>
> if (p->is_write) {
> switch (r->reg) {
> + case PMEVTYPER0_EL0 ... PMCCFILTR_EL0: {
Please don't do that, this is dangerous.
I'm fine with PMEVTYPER0_EL0 ... PMEVTYPER30_EL0, but not with
PMCCFILTR_EL0. It could have been moved to another offset in the
register file, and nobody would notice this. So keep it as a separate
case statement.
> + val = r->reg - PMEVTYPER0_EL0;
> + kvm_pmu_set_counter_event_type(vcpu, p->regval, val);
> + vcpu_sys_reg(vcpu, r->reg) = p->regval;
> + break;
> + }
> case PMCR_EL0: {
> /* Only update writeable bits of PMCR */
> val = vcpu_sys_reg(vcpu, r->reg);
> @@ -522,6 +528,13 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
> { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111), \
> trap_wcr, reset_wcr, n, 0, get_wcr, set_wcr }
>
> +/* Macro to expand the PMEVTYPERn_EL0 register */
> +#define PMU_PMEVTYPER_EL0(n) \
> + /* PMEVTYPERn_EL0 */ \
> + { Op0(0b11), Op1(0b011), CRn(0b1110), \
> + CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
> + access_pmu_regs, reset_unknown, (PMEVTYPER0_EL0 + n), }
> +
> /*
> * Architected system registers.
> * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
> @@ -736,6 +749,42 @@ static const struct sys_reg_desc sys_reg_descs[] = {
> { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
> NULL, reset_unknown, TPIDRRO_EL0 },
>
> + /* PMEVTYPERn_EL0 */
> + PMU_PMEVTYPER_EL0(0),
> + PMU_PMEVTYPER_EL0(1),
> + PMU_PMEVTYPER_EL0(2),
> + PMU_PMEVTYPER_EL0(3),
> + PMU_PMEVTYPER_EL0(4),
> + PMU_PMEVTYPER_EL0(5),
> + PMU_PMEVTYPER_EL0(6),
> + PMU_PMEVTYPER_EL0(7),
> + PMU_PMEVTYPER_EL0(8),
> + PMU_PMEVTYPER_EL0(9),
> + PMU_PMEVTYPER_EL0(10),
> + PMU_PMEVTYPER_EL0(11),
> + PMU_PMEVTYPER_EL0(12),
> + PMU_PMEVTYPER_EL0(13),
> + PMU_PMEVTYPER_EL0(14),
> + PMU_PMEVTYPER_EL0(15),
> + PMU_PMEVTYPER_EL0(16),
> + PMU_PMEVTYPER_EL0(17),
> + PMU_PMEVTYPER_EL0(18),
> + PMU_PMEVTYPER_EL0(19),
> + PMU_PMEVTYPER_EL0(20),
> + PMU_PMEVTYPER_EL0(21),
> + PMU_PMEVTYPER_EL0(22),
> + PMU_PMEVTYPER_EL0(23),
> + PMU_PMEVTYPER_EL0(24),
> + PMU_PMEVTYPER_EL0(25),
> + PMU_PMEVTYPER_EL0(26),
> + PMU_PMEVTYPER_EL0(27),
> + PMU_PMEVTYPER_EL0(28),
> + PMU_PMEVTYPER_EL0(29),
> + PMU_PMEVTYPER_EL0(30),
> + /* PMCCFILTR_EL0 */
> + { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b1111), Op2(0b111),
> + access_pmu_regs, reset_unknown, PMCCFILTR_EL0, },
> +
> /* DACR32_EL2 */
> { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
> NULL, reset_unknown, DACR32_EL2 },
> @@ -934,6 +983,12 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
>
> if (p->is_write) {
> switch (r->reg) {
> + case c14_PMEVTYPER0 ... c14_PMCCFILTR: {
Same problem here.
> + val = r->reg - c14_PMEVTYPER0;
> + kvm_pmu_set_counter_event_type(vcpu, p->regval, val);
> + vcpu_cp15(vcpu, r->reg) = p->regval;
> + break;
> + }
> case c9_PMCR: {
> /* Only update writeable bits of PMCR */
> val = vcpu_cp15(vcpu, r->reg);
> @@ -967,6 +1022,13 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
> return true;
> }
>
> +/* Macro to expand the PMEVTYPERn register */
> +#define PMU_PMEVTYPER(n) \
> + /* PMEVTYPERn */ \
> + { Op1(0), CRn(0b1110), \
> + CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
> + access_pmu_cp15_regs, NULL, (c14_PMEVTYPER0 + n), }
> +
> /*
> * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
> * depending on the way they are accessed (as a 32bit or a 64bit
> @@ -1022,6 +1084,42 @@ static const struct sys_reg_desc cp15_regs[] = {
> { Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
>
> { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
> +
> + /* PMEVTYPERn */
> + PMU_PMEVTYPER(0),
> + PMU_PMEVTYPER(1),
> + PMU_PMEVTYPER(2),
> + PMU_PMEVTYPER(3),
> + PMU_PMEVTYPER(4),
> + PMU_PMEVTYPER(5),
> + PMU_PMEVTYPER(6),
> + PMU_PMEVTYPER(7),
> + PMU_PMEVTYPER(8),
> + PMU_PMEVTYPER(9),
> + PMU_PMEVTYPER(10),
> + PMU_PMEVTYPER(11),
> + PMU_PMEVTYPER(12),
> + PMU_PMEVTYPER(13),
> + PMU_PMEVTYPER(14),
> + PMU_PMEVTYPER(15),
> + PMU_PMEVTYPER(16),
> + PMU_PMEVTYPER(17),
> + PMU_PMEVTYPER(18),
> + PMU_PMEVTYPER(19),
> + PMU_PMEVTYPER(20),
> + PMU_PMEVTYPER(21),
> + PMU_PMEVTYPER(22),
> + PMU_PMEVTYPER(23),
> + PMU_PMEVTYPER(24),
> + PMU_PMEVTYPER(25),
> + PMU_PMEVTYPER(26),
> + PMU_PMEVTYPER(27),
> + PMU_PMEVTYPER(28),
> + PMU_PMEVTYPER(29),
> + PMU_PMEVTYPER(30),
> + /* PMCCFILTR */
> + { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_cp15_regs,
> + NULL, c14_PMCCFILTR },
> };
>
> static const struct sys_reg_desc cp15_64_regs[] = {
>
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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