On Wed, Nov 18, 2015 at 10:20:14AM +0800, Huaitong Han wrote: > Changes in v3: > *Fix cpuid_7_0_ecx_feature_name error. > > Changes in v2: > *Fix memcpy error for xsave state. > *Fix TCG_7_0_ECX_FEATURES to 0. > *Make subjects more readable. > > The protection-key feature provides an additional mechanism by which IA-32e > paging controls access to usermode addresses. > > Hardware support for protection keys for user pages is enumerated with CPUID > feature flag CPUID.7.0.ECX[3]:PKU. Software support is CPUID.7.0.ECX[4]:OSPKE > with the setting of CR4.PKE(bit 22). > > The PKRU register is XSAVE-managed state CPUID.D.0.EAX[9], the size of XSAVE > state component for PKRU is 8 bytes, the offset is 0xa80. Is every CPU supporting PKU guaranteed to have CPUID.(EAX=0DH,ECX=9):EBX = 0xa80? Where is the PKRU state offset/layout documented? > > The specification of Protection Keys can be found at SDM (4.6.2, volume 3) > http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf. > [...] -- Eduardo -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
