Hi Drew,
I appreciate your feedback on these patches.
On 10/18/2015 02:28 PM, Andrew Jones wrote:
>> --- a/arm/pmu.c
>> +++ b/arm/pmu.c
>> @@ -37,6 +37,18 @@ static inline unsigned long get_pmccntr(void)
>> asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (cycles));
>> return cycles;
>> }
>> +
>> +static inline void loop(int i, uint32_t pmcr)
>> +{
>> + uint32_t z = 0;
>> +
>> + asm volatile(
>> + " mcr p15, 0, %[pmcr], c9, c12, 0\n"
>> + " 1: subs %[i], %[i], #1\n"
>> + " bgt 1b\n"
>> + " mcr p15, 0, %[z], c9, c12, 0\n"
>> + : [i] "+r" (i) : [pmcr] "r" (pmcr), [z] "r" (z) : "cc");
>
> Assembly is always ugly, but we can do a bit better formatting with tabs
>
> asm volatile(
> " mcr p15, 0, %[pmcr], c9, c12, 0\n"
> "1: subs %[i], %[i], #1\n"
> " bgt 1b\n"
> " mcr p15, 0, %[z], c9, c12, 0\n"
> : [i] "+r" (i)
> : [pmcr] "r" (pmcr), [z] "r" (z)
> : "cc");
>
> Actually it can be even cleaner because you already created set_pmcr()
>
> set_pmcr(pmcr);
>
> asm volatile(
> "1: subs %0, %0, #1\n"
> " bgt 1b\n"
> : "+r" (i) : : "cc");
>
> set_pmcr(0);
Is there any way to ensure that the compiler won't for example put a `mov rd,
#0` between the `bgt 1b` and the `mcr <pmcr>, rn`?
>> @@ -125,12 +147,79 @@ static bool check_cycles_increase(void)
>> return true;
>> }
>>
>> -int main(void)
>> +/*
>> + * Execute a known number of guest instructions. Only odd instruction counts
>> + * greater than or equal to 3 are supported by the in-line assembly code. The
>
> Not all odd counts, right? But rather all multiples of 3? IIUC this is because
> the loop is two instructions (sub + branch), and then the clearing of the pmcr
> register counts as the 3rd?
Clearing the PMCR doesn't happen as part of the loop, but as part of the loop
exit or epilogue.
total_instrs = iteration_count * loop_instrs + eipilogue_instrs
total_instrs = iteration_count * 2 + 1
Thanks,
Christopher Covington
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