On 2015/10/14 19:30, Paolo Bonzini wrote:
On 14/10/2015 13:26, Jian Zhou wrote:
On 12/10/2015 20:44, Paolo Bonzini wrote:
In addition, the MSR numbers may differ between the guest and the host,
because it is possible to emulate e.g. a Core CPU on a Core 2 CPU. So I
recommend against using the atomic switch mechanism for the from/to MSRs.
The vLBR feature depends on vPMU, and to enable vPMU, it needs to
specify the "cpu mode" in the guest XML as host-passthrough. I think
the MSR numbers between the guest and the host are the same in this
senario.
Does it depend on vPMU _for Linux guests_ or in general? My impression
is that LBR can be used by the guest independent of the PMU.
I think only for Linux guests.
I googled how to enable LBR on other guests(except Linux guests),
e.g. Windows, and got no developer manuals about it.
Here is an article about it:
http://www.codeproject.com/Articles/517466/Last-branch-records-
and-branch-tracing
it says:
"bit 8 of DR7 represents bit 0 of DebugCtl. This is the LBR bit."
Intel developer manual vol 3B introduced DR7(Debug Control Register)
and bit 8 of it on Section 17.2.4:
"LE and GE (local and global exact breakpoint enable) flags (bits 8,
9) — When set, these flags cause the processor to detect the exact
instruction that caused a data breakpoint condition. For backward and
forward compatibility with other Intel processors, we recommend that
the LE and GE flags be set to 1 if exact breakpoints are required."
But for now, I don't know how to test bit 8 of DR7 on Windows.
Regards,
Jian
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