On Fri, May 29, 2015 at 06:44:44PM +1000, Alexey Kardashevskiy wrote: > At the moment the DMA setup code looks for the "ibm,opal-tce-kill" > property which contains the TCE kill register address. Writing to > this register invalidates TCE cache on IODA/IODA2 hub. > > This moves the register address from iommu_table to pnv_pnb as this > register belongs to PHB and invalidates TCE cache for all tables of > all attached PEs. > > This moves the property reading/remapping code to a helper which is > called when DMA is being configured for PE and which does DMA setup > for both IODA1 and IODA2. > > This adds a new pnv_pci_ioda2_tce_invalidate_entire() helper which > invalidates cache for the entire table. It should be called after > every call to opal_pci_map_pe_dma_window(). It was not required before > because there was just a single TCE table and 64bit DMA was handled via > bypass window (which has no table so no cache was used) but this is going > to change with Dynamic DMA windows (DDW). > > Signed-off-by: Alexey Kardashevskiy <aik@xxxxxxxxx> Reviewed-by: David Gibson <david@xxxxxxxxxxxxxxxxxxxxx> -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
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