On 03/17/2015 02:19 AM, Jan Kiszka wrote:
> On 2015-03-17 02:30, James Sullivan wrote:
>> Changes Since v1:
>> * Reworked patches into two commits:
>> 1) [Patch v2 1/2] Extended struct kvm_lapic_irq with bool
>> msi_redir_hint
>> * Initialize msi_redir_hint = true in kvm_set_msi_irq when RH=1
>> * Initialize msi_redir_hint = false otherwise
>> * Added value of msi_redir_hint to debug message dump of IRQ in
>> apic_send_ipi
>> 2) [Patch v2 2/2] Deliver to only lowest prio CPU if msi_redir_hint
>> is true
>> * Move kvm_is_dm_lowest_prio() -> lapic.h, rename to
>> kvm_lowest_prio_delivery, set condition to
>> (APIC_DM_LOWPRI || msi_redir_hint)
>> * Change check in kvm_irq_delivery_to_apic_fast() for
>> APIC_DM_LOWPRI or msi_redir_hint to a check for
>> kvm_is_dm_lowest_prio()
>> Changes since v2:
>> * Extend Patch 1/2 ("kvm: x86: Extended struct kvm_lapic_irq with
>> msi_redir_hint for MSI delivery") with older patch to set the value
>> of dest_mode in kvm_set_msi_irq() to be APIC_DEST_LOGICAL only when
>> RH=1/DM=1, and APIC_DEST_PHYSICAL otherwise.
>> (<5502FEDB.3030606@xxxxxxxxx>)
>> This was done to decouple the patch dependency and to collect all
>> efforts to implement RH bit handling into one submission.
>> * Patch formatting
>>
>> This series of patches extends the KVM interrupt delivery mechanism
>> to correctly account for the MSI Redirection Hint bit. The RH bit is
>> used in logical destination mode to indicate that the delivery of the
>> interrupt shall only be to the lowest priority candidate LAPIC.
>>
>> Currently, there is no handling of the MSI RH bit in the KVM interrupt
>> delivery mechanism. This patch implements the following logic:
>>
>> * DM=0, RH=* : Physical destination mode. Interrupt is delivered to
>> the LAPIC with the matching APIC ID. (Subject to
>> the usual restrictions, i.e. no broadcast dest)
>> * DM=1, RH=0 : Logical destination mode without redirection. Interrupt
>> is delivered to all LAPICs in the logical group
>> specified by the IRQ's destination map and delivery
>> mode.
>> * DM=1, RH=1 : Logical destination mode with redirection. Interrupt
>> is delivered only to the lowest priority LAPIC in the
>> logical group specified by the dest map and the
>> delivery mode. Delivery semantics are otherwise
>> specified by the delivery_mode of the IRQ, which
>> is unchanged.
>>
>> In other words, the RH bit is ignored in physical destination mode, and
>> when it is set in logical destination mode causes delivery to only apply
>> to the lowest priority processor in the logical group. The IA32 manual
>> is in slight contradiction with itself on this matter, but this patch
>> agrees with this interpretation of the RH bit:
>>
>> https://software.intel.com/en-us/forums/topic/288883
>>
>> This patch has passed some rudimentary tests using an SMP QEMU guest and
>> virtio sourced MSIs, but I haven't done experiments with passing through
>> PCI hardware (intend to start working on this).
>
> Once the kernel side is settled, would you mind looking into equivalent
> support for QEMU's APIC as well? Just to keep it easy to switch between
> both modes without too many functional restrictions.
>
> Thanks!
> Jan
>
Just an update- I've submitted this to the QEMU side of things, see
https://lists.gnu.org/archive/html/qemu-devel/2015-03/msg05020.html
-James
--
To unsubscribe from this list: send the line "unsubscribe kvm" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at http://vger.kernel.org/majordomo-info.html
