2015-03-19 16:51-0600, James Sullivan: > I played around with native_compose_msi_msg and discovered the following: > > * dm=0, rh=0 => Physical Destination Mode > * dm=0, rh=1 => Failed delivery > * dm=1, rh=0 => Logical Destination Mode, No Redirection > * dm=1, rh=1 => Logical Destination Mode, Redirection Great! (What CPU family was that?) > So it seems to be the case that logical destination mode is used whenever > DM=1, regardless of RH. Furthermore, the case where DM=0 and RH=1 is > undefined, as was indicated in the closing response to the thread in > https://software.intel.com/en-us/forums/topic/288883 : DM=0+RH=1 might be defined to "fail", but I think it's acceptable to treat it as undefined. (Deliver them in KVM if it improves something.) I'm still wondering about last sentence from that link, the parenthesised part to be exact, The reference to the APIC ID being 0xff is because 0xff is broadcast and lowest priority (what the RH bit really is for X86) is illegal with broadcast. Can you also check if RH=1 does something to delivery mode? Thanks. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
