With APICv, LAPIC timer interrupt is always delivered via IRR:
apic_find_highest_irr syncs PIR to IRR.
Signed-off-by: Marcelo Tosatti <mtosatti@xxxxxxxxxx>
---
arch/x86/kvm/lapic.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
Index: kvm/arch/x86/kvm/lapic.c
===================================================================
--- kvm.orig/arch/x86/kvm/lapic.c 2015-02-02 14:57:19.903066983 -0200
+++ kvm/arch/x86/kvm/lapic.c 2015-02-02 15:25:40.197299923 -0200
@@ -1086,13 +1086,13 @@
if (kvm_apic_hw_enabled(apic)) {
int vec = reg & APIC_VECTOR_MASK;
+ void *bitmap = apic->regs + APIC_ISR;
- if (kvm_x86_ops->test_posted_interrupt)
- return kvm_x86_ops->test_posted_interrupt(vcpu, vec);
- else {
- if (apic_test_vector(vec, apic->regs + APIC_ISR))
- return true;
- }
+ if (kvm_x86_ops->deliver_posted_interrupt)
+ bitmap = apic->regs + APIC_IRR;
+
+ if (apic_test_vector(vec, bitmap))
+ return true;
}
return false;
}
--
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