Sprinkle in some more isbs after context-changing operations, as the ARM ARM states we should. I haven't seen any problems without them, but we should do it right. Also, *actually* set the MAIR in asm_mmu_enable. We were reading, not writing... Luckily this was just spotted while adding the isbs, rather than leading to a nightmare debug session some day... Signed-off-by: Andrew Jones <drjones@xxxxxxxxxx> --- arm/cstart.S | 8 ++++++-- lib/arm/processor.c | 1 + 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arm/cstart.S b/arm/cstart.S index da496e9eae7e0..39fac8f1e1bd8 100644 --- a/arm/cstart.S +++ b/arm/cstart.S @@ -50,6 +50,7 @@ start: .macro set_mode_stack mode, stack add \stack, #S_FRAME_SIZE msr cpsr_c, #(\mode | PSR_I_BIT | PSR_F_BIT) + isb mov sp, \stack .endm @@ -70,6 +71,7 @@ exceptions_init: set_mode_stack FIQ_MODE, r1 msr cpsr_cxsf, r2 @ back to svc mode + isb mov pc, lr .text @@ -96,12 +98,13 @@ asm_mmu_enable: /* MAIR */ ldr r2, =PRRR - mrc p15, 0, r2, c10, c2, 0 + mcr p15, 0, r2, c10, c2, 0 ldr r2, =NMRR - mrc p15, 0, r2, c10, c2, 1 + mcr p15, 0, r2, c10, c2, 1 /* TTBR0 */ mcrr p15, 0, r0, r1, c2 + isb /* SCTLR */ mrc p15, 0, r2, c1, c0, 0 @@ -109,6 +112,7 @@ asm_mmu_enable: orr r2, #CR_I orr r2, #CR_M mcr p15, 0, r2, c1, c0, 0 + isb mov pc, lr diff --git a/lib/arm/processor.c b/lib/arm/processor.c index da4163664a835..f8bd94cbb8bc6 100644 --- a/lib/arm/processor.c +++ b/lib/arm/processor.c @@ -115,6 +115,7 @@ void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr) "bic r0, #" xstr(MODE_MASK) "\n" "orr r0, #" xstr(USR_MODE) "\n" "msr cpsr_c, r0\n" + "isb\n" "mov r0, %0\n" "mov sp, %1\n" "mov pc, %2\n" -- 1.9.3 -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
