2014-11-26 17:11+0200, Nadav Amit:
> x2APIC has no registers for DFR and ICR (see Intel SDM 10.12.1.2 "x2APIC
> Register Address Space"). KVM needs to cause #GP on such accesses.
We should to take care of write to ICR2 as well.
> Fix it.
>
> Signed-off-by: Nadav Amit <namit@xxxxxxxxxxxxxxxxx>
> ---
> arch/x86/kvm/lapic.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index e0e5642..7611b75 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -1897,6 +1897,12 @@ int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
> if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
> return 1;
>
> + if (reg == APIC_DFR || reg == APIC_ICR2) {
> + apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
> + reg);
> + return 1;
> + }
> +
> if (apic_reg_read(apic, reg, 4, &low))
> return 1;
> if (msr == 0x830)
> --
> 1.9.1
>
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