On Sun, Aug 24, 2014 at 5:38 PM, Gleb Natapov <gleb@xxxxxxxxxx> wrote:
> On Sun, Aug 24, 2014 at 11:54:32AM +0800, Dennis Chen wrote:
>> This patch is used to construct the eptp in vmx mode with values
>> readed from MSR according to the intel x86 software developer's
>> manual.
>>
>> static u64 construct_eptp(unsigned long root_hpa)
>> {
>> - u64 eptp;
>> + u64 eptp, pwl;
>> +
>> + if (cpu_has_vmx_ept_4levels())
>> + pwl = VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
>> + else {
>> + WARN(1, "Unsupported page-walk length of 4.\n");
> Page-walk length of 4 is the only one that is supported.
>
Since there is a bit 6 in IA32_VMX_EPT_VPID_CAP MSR indicating the
support for the page-walk length, I think sanity check is necessary.
But I just checked the code, it's already done in the hardware_setup()
function which will disable ept feature if the page-wake length is not
4. Gleb, any comments for the memory type check part?
>> + BUG();
>> + }
>> +
>> + if (cpu_has_vmx_eptp_writeback())
>> + eptp = VMX_EPT_DEFAULT_MT | pwl;
>> + else if (cpu_has_vmx_eptp_uncacheable())
>> + eptp = VMX_EPT_UC_MT | pwl;
>> + else {
>> + WARN(1, "Unsupported memory type config in vmx eptp.\n");
>> + BUG();
>> + }
>>
>> - /* TODO write the value reading from MSR */
>> - eptp = VMX_EPT_DEFAULT_MT |
>> - VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
>> if (enable_ept_ad_bits)
>> eptp |= VMX_EPT_AD_ENABLE_BIT;
>> eptp |= (root_hpa & PAGE_MASK);
>> --
>> 1.7.9.5
>
> --
> Gleb.
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