On Thu, Jul 31, 2014 at 09:47:12AM +0000, Igor Mammedov wrote: > Due to erratum #778 from > "Revision Guide for AMD Family 15h Models 10h-1Fh Processors, > Publication # 48931, Issue Date: May 2013, Revision: 3.10" > > TSC on affected processor, a core may drift under certain conditions, > which makes initially synchronized TSCs to become unsynchronized. > > As result TSC clocksource becomes unsuitable for using as wallclock > and it brakes pvclock when it's running with PVCLOCK_TSC_STABLE_BIT > flag set. > That causes backwards clock jumps when pvclock is first read on > CPU with drifted TSC and then on CPU where TSC was stable or had > a lower drift rate. > > To fix issue mark TSC as unstable on affected CPU, so it won't > be used as clocksource. Which in turn disables master_clock > mechanism in KVM and force pvclock using global clock counter > that can't go backwards. > > Signed-off-by: Igor Mammedov <imammedo@xxxxxxxxxx> Acked-by: Borislav Petkov <bp@xxxxxxx> -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
