On Wed, May 7, 2014 at 11:58 AM, Paolo Bonzini <pbonzini@xxxxxxxxxx> wrote: > Il 04/05/2014 18:33, Hu Yaohui ha scritto: > >>> I experienced a similar problem that was related to nested code >>> having some bugs related to apicv and other new vmx features. >>> >>> For example, the code enabled posted interrupts to run L2 even when the >>> feature was not exposed to L1 and L1 didn't use it. >>> >>> Try changing prepare_vmcs02 to force disabling posted_interrupts, >>> code should looks like: >>> >>> .... >>> .... >>> exec_control = vmcs12->pin_based_vm_exec_control; >>> exec_control |= vmcs_config.pin_based_exec_ctrl; >>> exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER|PIN_BASED_POSTED_INTR); >>> vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control); >>> .... >>> ... >>> >>> and also >>> >>> ... >>> ... >>> exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | >>> SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | >>> SECONDARY_EXEC_APIC_REGISTER_VIRT | >>> SECONDARY_EXEC_PAUSE_LOOP_EXITING); > > > PLE should be left enabled, I think. Well... the PLE settings L0 uses to run L1 (vmcs01) may be different than the PLE settings L1 configured to run L2 (vmcs12). For example, L0 can use a ple_gap to run L1 that is bigger than the ple_gap L1 configured to run L2. Or L0 can use a ple_window to run L1 that is smaller than the ple_window L1 configured to run L2. So seems PLE should never be exposed to L1 or an appropriate nested handling needs to be implemented. Note the handling may become complex because in some cases a PLE exit from L2 should be handled directly by L0 and not passed to L1... remember nested preemption timer support :) ? > > Apart from that, I'll change the suggestion into a patch. Great! > > Thanks! > > Paolo > -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
