On Fri, 2014-05-02 at 13:10 +0200, Alexander Graf wrote: > On 05/02/2014 12:12 PM, David Laight wrote: > > You also probably want the page mapped uncached - no point polluting the data > > cache. We can't do that without creating an architecturally illegal alias between cacheable and non-cacheable mappings. > Do e500 chips have a shared I/D cache somewhere? Yes. Only L1 is separate. -Scott -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
