> From: Oliver O'Halloran <oohall@xxxxxxxxx> > Sent: Friday, July 29, 2022 10:53 AM > > On Fri, Jul 29, 2022 at 12:21 PM Alexey Kardashevskiy <aik@xxxxxxxxx> wrote: > > > > *snip* > > > > About this. If a platform has a concept of explicit DMA windows (2 or > > more), is it one domain with 2 windows or 2 domains with one window > each? > > > > If it is 2 windows, iommu_domain_ops misses windows manipulation > > callbacks (I vaguely remember it being there for embedded PPC64 but > > cannot find it quickly). > > > > If it is 1 window per a domain, then can a device be attached to 2 > > domains at least in theory (I suspect not)? > > > > On server POWER CPUs, each DMA window is backed by an independent > IOMMU > > page table. (reminder) A window is a bus address range where devices are > > allowed to DMA to/from ;) > > I've always thought of windows as being entries to a top-level "iommu > page table" for the device / domain. The fact each window is backed by > a separate IOMMU page table shouldn't really be relevant outside the > arch/platform. Yes. This is what was agreed when discussing how to integrate iommufd with POWER [1]. One domain represents one address space. Windows are just constraints on the address space for what ranges can be mapped. having two page tables underlying is just kind of POWER specific format. Thanks Kevin [1] https://lore.kernel.org/all/Yns+TCSa6hWbU7wZ@yekko/
