On 12/2/21 03:00, Sean Christopherson wrote:
Hmm, that suggests the bug/erratum is due to the CPU consuming stale data from #4
for the IsRunning check in #5, or retiring uops for the IsRunning check before
retiring the vIRR update.
Yes, this seems to be an error in the implementation of step 5. In
assembly, atomic operations have implicit memory barriers, but who knows
what's going on in microcode. So either it's the former, or something
is going on that's specific to the microcode sequencer, or it's a more
mundane implementation bug.
In any case, AVIC is disabled for now and will need a list of model
where it works, so I'll go on and queue the first part of this series.
Paolo
It would be helpful if the erratum actually provided
info on the "highly specific and detailed set of internal timing conditions". :-/
4. Lookup the vAPIC backing page address in the Physical APIC table using the
guest physical APIC ID as an index into the table.
5. For every valid destination:
- Atomically set the appropriate IRR bit in each of the destinations’ vAPIC
backing page.
- Check the IsRunning status of each destination.
