Fabiano Rosas <farosas@xxxxxxxxxxxxx> writes:
> Nicholas Piggin <npiggin@xxxxxxxxx> writes:
>
>> The TIDR SPR only exists on POWER9. Avoid accessing it when the
>> feature bit for it is not set.
>
> Not related to this patch, but how does this work with compat mode? A P9
> compat mode guest would get an invalid instruction when trying to access
> this SPR?
Good question.
I assume you're talking about P9 compat mode on P10.
In general compat mode only applies to userspace, because it's
implemented by setting the PCR which only (mostly?) applies to PR=1.
I don't think there's any special casing in the ISA for the TIDR, so I
think it just falls into the unimplemented SPR case for mt/fspr.
That's documented in Book III section 5.4.4, in particular on page 1171
it says:
Execution of this instruction specifying an SPR number
that is undefined for the implementation causes one of
the following.
• if spr[0]=0:
- if MSR[PR]=1: Hypervisor Emulation Assistance interrupt
- if MSR[PR]=0: Hypervisor Emulation Assistance interrupt for SPR
0,4,5, and 6, and no operation (i.e., the instruction is treated
as a no-op) when LPCR[EVIRT]=0 and Hypervisor Emulation Assistance
interrupt when LPCR[EVIRT]=1 for all other SPRs
Linux doesn't set EVIRT, and I assume neither does phyp, so it behaves
like a nop.
We actually use that behaviour in xmon to detect that an SPR is not
implemented, by noticing that the mfspr has no effect on the target
register, see dump_one_spr().
We should really write some docs on compat mode in the linuxppc wiki
and/or Documentation ;)
cheers
