Excerpts from Nicholas Piggin's message of April 2, 2021 1:03 am: > POWER9 and later processors always go via the P9 guest entry path now. > Remove the remaining support from the P7/8 path. > > Signed-off-by: Nicholas Piggin <npiggin@xxxxxxxxx> [...] > @@ -2527,28 +2259,14 @@ BEGIN_FTR_SECTION > END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) > > kvm_nap_sequence: /* desired LPCR value in r5 */ > -BEGIN_FTR_SECTION > - /* > - * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset) > - * enable state loss = 1 (allow SMT mode switch) > - * requested level = 0 (just stop dispatching) > - */ > - lis r3, (PSSCR_EC | PSSCR_ESL)@h > /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */ > li r4, LPCR_PECE_HVEE@higher > sldi r4, r4, 32 > or r5, r5, r4 > -FTR_SECTION_ELSE > - li r3, PNV_THREAD_NAP ^^^^^^^ > -ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) > mtspr SPRN_LPCR,r5 > isync > > -BEGIN_FTR_SECTION > - bl isa300_idle_stop_mayloss > -FTR_SECTION_ELSE > bl isa206_idle_insn_mayloss > -ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300) Got a bug or two in the old path because I didn't test SMT configs. I'll work through those so for now don't spend too much time trying to run the old path or going through the rmhandlers.S asm changes in the series until I post the next round. Thanks, Nick
