On Sun, 22 Nov 2020 18:39:50 +1100
Alexey Kardashevskiy <aik@xxxxxxxxx> wrote:
> We execute certain NPU2 setup code (such as mapping an LPID to a device
> in NPU2) unconditionally if an Nvlink bridge is detected. However this
> cannot succeed on POWER8NVL machines as the init helpers return an error
> other than ENODEV which means the device is there is and setup failed so
> vfio_pci_enable() fails and pass through is not possible.
>
> This changes the two NPU2 related init helpers to return -ENODEV if
> there is no "memory-region" device tree property as this is
> the distinction between NPU and NPU2.
>
> Tested on
> - POWER9 pvr=004e1201, Ubuntu 19.04 host, Ubuntu 18.04 vm,
> NVIDIA GV100 10de:1db1 driver 418.39
> - POWER8 pvr=004c0100, RHEL 7.6 host, Ubuntu 16.10 vm,
> NVIDIA P100 10de:15f9 driver 396.47
>
> Fixes: 7f92891778df ("vfio_pci: Add NVIDIA GV100GL [Tesla V100 SXM2] subdriver")
> Cc: stable@xxxxxxxxxxxxxxx # 5.0
> Signed-off-by: Alexey Kardashevskiy <aik@xxxxxxxxx>
> ---
> Changes:
> v2:
> * updated commit log with tested configs and replaced P8+ with POWER8NVL for clarity
> ---
> drivers/vfio/pci/vfio_pci_nvlink2.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
Thanks, applies to vfio next branch for v5.11.
Alex
>
> diff --git a/drivers/vfio/pci/vfio_pci_nvlink2.c b/drivers/vfio/pci/vfio_pci_nvlink2.c
> index 65c61710c0e9..9adcf6a8f888 100644
> --- a/drivers/vfio/pci/vfio_pci_nvlink2.c
> +++ b/drivers/vfio/pci/vfio_pci_nvlink2.c
> @@ -231,7 +231,7 @@ int vfio_pci_nvdia_v100_nvlink2_init(struct vfio_pci_device *vdev)
> return -EINVAL;
>
> if (of_property_read_u32(npu_node, "memory-region", &mem_phandle))
> - return -EINVAL;
> + return -ENODEV;
>
> mem_node = of_find_node_by_phandle(mem_phandle);
> if (!mem_node)
> @@ -393,7 +393,7 @@ int vfio_pci_ibm_npu2_init(struct vfio_pci_device *vdev)
> int ret;
> struct vfio_pci_npu2_data *data;
> struct device_node *nvlink_dn;
> - u32 nvlink_index = 0;
> + u32 nvlink_index = 0, mem_phandle = 0;
> struct pci_dev *npdev = vdev->pdev;
> struct device_node *npu_node = pci_device_to_OF_node(npdev);
> struct pci_controller *hose = pci_bus_to_host(npdev->bus);
> @@ -408,6 +408,9 @@ int vfio_pci_ibm_npu2_init(struct vfio_pci_device *vdev)
> if (!pnv_pci_get_gpu_dev(vdev->pdev))
> return -ENODEV;
>
> + if (of_property_read_u32(npu_node, "memory-region", &mem_phandle))
> + return -ENODEV;
> +
> /*
> * NPU2 normally has 8 ATSD registers (for concurrency) and 6 links
> * so we can allocate one register per link, using nvlink index as
