On Thu, Jul 16, 2020 at 01:32:13AM -0700, Ram Pai wrote: > An instruction accessing a mmio address, generates a HDSI fault. This fault is > appropriately handled by the Hypervisor. However in the case of secureVMs, the > fault is delivered to the ultravisor. > > Unfortunately the Ultravisor has no correct-way to fetch the faulting > instruction. The PEF architecture does not allow Ultravisor to enable MMU > translation. Walking the two level page table to read the instruction can race > with other vcpus modifying the SVM's process scoped page table. > > This problem can be correctly solved with some help from the kernel. > > Capture the faulting instruction in SPRG0 register, before executing the > faulting instruction. This enables the ultravisor to easily procure the > faulting instruction and emulate it. Just a comment on the approach of putting the instruction in SPRG0: these I/O accessors can be used in interrupt routines, which means that if these accessors are ever used with interrupts enabled, there is the possibility of an external interrupt occurring between the instruction that sets SPRG0 and the load/store instruction that faults. If the handler for that interrupt itself does an I/O access, it will overwrite SPRG0, corrupting the value set by the interrupted code. The choices to fix that would seem to be (a) disable interrupts around all I/O accesses, (b) have the accessor save and restore SPRG0, or (c) solve the problem another way, such as by doing a H_LOGICAL_CI_LOAD or H_LOGICAL_CI_STORE hypercall. Paul.
