On Mon, Feb 17, 2020 at 05:23:07PM +1100, Michael Neuling wrote: > > > Hence, we should NOP this, not generate an illegal. > > > > It is not a reserved bit. > > > > The IMC entry for it matches op1=011111 op2=1////01110 presumably, which > > catches all TM instructions and nothing else (bits 0..5 and bits 21..30). > > That does not look at bit 31, the softpatch handler has to deal with this. > > > > Some TM insns have bit 31 as 1 and some have it as /. All instructions > > with a "." in the mnemonic have bit 31 is 1, all other have it reserved. > > The tables in appendices D, E, F show tend. and tsr. as having it > > reserved, which contradicts the individual instruction description (and > > does not make much sense). (Only tcheck has /, everything else has 1; > > everything else has a mnemonic with a dot, and does write CR0 always). > > Wow, interesting. > > P8 seems to be treating 31 as a reserved bit (with the table definition rather > than the individual instruction description). I'm inclined to match P8 even > though it's inconsistent with the dot mnemonic as you say. "The POWER8 core ignores the state of reserved bits in the instructions (denoted by “///” in the instruction definition) and executes the instruction normally. Software should set these bits to ‘0’ per the Power ISA." (p8 UM, 3.1.1.3; same in the p9 UM). Segher
