For now, disable hardware PMU facilities in secure virtual
machines (SVMs) to prevent any information leak between SVMs
and the (untrusted) HV.
With this, a simple 'myperf' program that uses the perf_event_open()
fails for SVMs (with the corresponding fix to UV). In normal VMs and
on the bare-metal HV the syscall and performance counters work
Signed-off-by: Sukadev Bhattiprolu <sukadev@xxxxxxxxxxxxx>
---
arch/powerpc/kernel/cpu_setup_power.S | 22 ++++++++++++++++++++++
arch/powerpc/perf/core-book3s.c | 6 ++++++
2 files changed, 28 insertions(+)
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S
index a460298c7ddb..d5eb06e20b5a 100644
--- a/arch/powerpc/kernel/cpu_setup_power.S
+++ b/arch/powerpc/kernel/cpu_setup_power.S
@@ -206,14 +206,36 @@ __init_PMU_HV_ISA207:
blr
__init_PMU:
+#ifdef CONFIG_PPC_SVM
+ /*
+ * For now, SVM's are restricted from accessing PMU
+ * features, so skip accordingly.
+ */
+ mfmsr r5
+ rldicl r5, r5, 64-MSR_S_LG, 62
+ cmpwi r5,1
+ beq skip1
+#endif
li r5,0
mtspr SPRN_MMCRA,r5
mtspr SPRN_MMCR0,r5
mtspr SPRN_MMCR1,r5
mtspr SPRN_MMCR2,r5
+skip1:
blr
__init_PMU_ISA207:
+#ifdef CONFIG_PPC_SVM
+ /*
+ * For now, SVM's are restricted from accessing PMU
+ * features, so skip accordingly.
+ */
+ mfmsr r5
+ rldicl r5, r5, 64-MSR_S_LG, 62
+ cmpwi r5,1
+ beq skip2
+#endif
li r5,0
mtspr SPRN_MMCRS,r5
+skip2:
blr
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 4e76b2251801..9e6a9f1803f6 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -2275,6 +2275,12 @@ static int power_pmu_prepare_cpu(unsigned int cpu)
int register_power_pmu(struct power_pmu *pmu)
{
+ /*
+ * PMU events are not currently supported in SVMs
+ */
+ if (is_secure_guest())
+ return -ENOSYS;
+
if (ppmu)
return -EBUSY; /* something's already registered */
--
2.17.2
