Nicholas Piggin <npiggin@xxxxxxxxx> writes: > Claudio Carvalho's on June 29, 2019 6:08 am: >> From: Sukadev Bhattiprolu <sukadev@xxxxxxxxxxxxxxxxxx> >> >> The ultravisor processor mode is introduced in POWER platforms that >> supports the Protected Execution Facility (PEF). Ultravisor is higher >> privileged than hypervisor mode. >> >> In PEF enabled platforms, the MSR_S bit is used to indicate if the >> thread is in secure state. With the MSR_S bit, the privilege state of >> the thread is now determined by MSR_S, MSR_HV and MSR_PR, as follows: >> >> S HV PR >> ----------------------- >> 0 x 1 problem >> 1 0 1 problem >> x x 0 privileged >> x 1 0 hypervisor >> 1 1 0 ultravisor >> 1 1 1 reserved > > What does this table mean? I thought 'x' meant either, but in that > case there are several states that can apply to the same > combination of bits. > > Would it be clearer to rearrange the table so the columns are the HV > and PR bits we know and love, plus the effect of S=1 on each of them? > > HV PR S=0 S=1 > --------------------------------------------- > 0 0 privileged privileged (secure guest kernel) > 0 1 problem problem (secure guest userspace) > 1 0 hypervisor ultravisor > 1 1 problem reserved > > Is that accurate? I like that format. cheers
