On Mon, Jul 01, 2019 at 04:30:55PM +1000, Alexey Kardashevskiy wrote: > > > On 01/07/2019 16:17, maddy wrote: > > > > On 01/07/19 11:24 AM, Alexey Kardashevskiy wrote: > >> > >> On 29/06/2019 06:08, Claudio Carvalho wrote: > >>> When the ultravisor firmware is available, it takes control over the > >>> LDBAR register. In this case, thread-imc updates and save/restore > >>> operations on the LDBAR register are handled by ultravisor. > >> What does LDBAR do? "Power ISA™ Version 3.0 B" or "User’s Manual POWER9 > >> Processor" do not tell. > > LDBAR is a per-thread SPR used by thread-imc pmu to dump the counter > > data into memory. > > LDBAR contains memory address along with few other configuration bits > > (it is populated > > by the thread-imc pmu driver). It is populated and enabled only when any > > of the thread > > imc pmu events are monitored. > > > I was actually looking for a spec for this register, what is the > document name? Its not a architected register. Its documented in the Power9 workbook. RP
